Array Substrate Layout for LCD Mura-Free Polarity Inversion
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Solution Overview
Problem
In dual gate LCD structures, the uniformity of voltage polarity across sub-pixels leads to undesirable mura phenomena due to alternating voltage polarities, and methods like dot inversion increase power consumption and reduce display effectiveness.
Innovation Solution
An array substrate design with alternating first and second extensions in data lines, combined with compensation blocks and integrated gate lines, reverses the polarity of sub-pixels to prevent mura while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If dot inversion method is used to eliminate mura phenomenon, then the mura phenomenon is eliminated, but power consumption increases sharply
Solution Approach 1:
The patent applies dot inversion by arranging sub-pixels in alternating patterns (first sub-pixel type, second sub-pixel type, first sub-pixel type, etc.) along the data line direction, causing adjacent sub-pixels to have opposite voltage polarities. This inversion eliminates the mura phenomenon while avoiding continuous charging of the same sub-pixel, thus preventing excessive power consumption increase.
Solution Approach 2:
The patent segments the pixel array into different types of pixel areas (first pixel areas with two sub-pixels, second pixel areas with one sub-pixel) arranged in an alternating pattern. This segmentation allows different charging strategies for different sub-pixel types, enabling polarity averaging to eliminate mura while controlling power consumption through selective arrangement rather than uniform dot inversion across all pixels.
2Area of stationary object
If dual gate structure is used to drive sub-pixels, then screen-to-body ratio is increased, but mura phenomenon occurs due to voltage polarity uniformity
Solution Approach 1:
The patent introduces asymmetry in the pixel arrangement by creating two types of pixel areas: first pixel areas containing two sub-pixels and second pixel areas containing one sub-pixel. These are arranged alternately in the display panel, creating an asymmetric pattern that breaks the voltage polarity uniformity caused by the dual gate structure, thereby eliminating mura while preserving the high screen-to-body ratio benefit.
Solution Approach 2:
The patent applies local quality by assigning different sub-pixel configurations to different regions (first pixel areas vs. second pixel areas). Instead of using a uniform structure throughout, the local arrangement of sub-pixels is varied to create alternating voltage polarity patterns that eliminate mura, while each local region still benefits from the dual gate driving structure for high screen-to-body ratio.
Data Source
AI summary
An array substrate and display device are provided. The array substrate includes a base substrate, and gate lines, data lines, compensation blocks and sub-pixels located on the base substrate. Two gate lines are arranged between two adjacent rows of sub-pixels. The data lines are provided with multiple first extensions and second extensions arranged alternately. The extending direction of the first extensions intersects with the extending direction of the second extensions. The gate lines and data lines define multiple first pixel areas and second pixel areas on the base substrate. Two sub-pixels are arranged in the first pixel area, and one sub-pixel is arranged in the second pixel area. The multiple first pixel areas are arranged in an array, the multiple second pixel areas are arranged in two columns, and multiple columns of the first pixel areas are located between the two columns of the second pixel areas.