Array Substrate with Polycrystalline Silicon and Metal Oxide TFTs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current array substrates for display devices, such as LCDs and OLEDs, face challenges in achieving optimal performance due to limitations in thin film transistor (TFT) design and material selection, which affect electron mobility and leakage current, particularly in large-size display panels.
Innovation Solution
The array substrate incorporates multiple types of thin film transistors (TFTs) with channel layers made of polycrystalline silicon and metal oxide materials, along with a layered structure including insulator and gate electrodes, to enhance electron mobility and reduce leakage current, while also using doping processes to optimize TFT performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TFT design and material selection are used, then manufacturing simplicity is maintained, but electron mobility is insufficient and leakage current increases
Solution Approach 1:
The patent employs composite material structures in TFT channel layers, combining polycrystalline silicon with metal oxide materials (such as IGZO - indium gallium zinc oxide) to create multi-layer channel structures. This composite approach enables the device to achieve high electron mobility (exceeding 10 cm²/Vs) while maintaining controlled leakage current, directly resolving the contradiction between performance and structural simplicity.
Solution Approach 2:
The invention implements local quality optimization by creating distinct regions within the TFT structure with different material compositions and doping levels. Specifically, the channel layer features varying concentrations of dopants (phosphorus, boron) at different depths and lateral positions, allowing localized enhancement of electron mobility in critical regions while maintaining overall device control and reducing unwanted leakage pathways.
2Reliability
If advanced TFT designs with multiple materials are used, then electron mobility improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing selective doping and material deposition in predetermined sequences during fabrication. The process involves pre-forming buffer layers, followed by controlled deposition of polycrystalline silicon and metal oxide layers with specific thicknesses and compositions. This staged approach, including pre-annealing treatments and sequential doping steps, enables complex multi-material TFT structures to be manufactured systematically, reducing overall fabrication complexity while achieving superior leakage current control.
Solution Approach 2:
The invention utilizes parameter changes by systematically varying material composition ratios, layer thicknesses, and doping concentrations to optimize TFT performance. Specifically, the metal oxide layer composition (e.g., In:Ga:Zn ratios in IGZO) and dopant concentrations are precisely controlled within defined ranges to achieve the desired balance between low leakage current and high electron mobility, enabling performance optimization without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical properties and display efficiency of the array substrate, enabling better performance in both LCD and OLED devices, particularly in large-size panels by achieving higher charge carrier mobility and reducing fabrication costs.
Implementation Method 1
using doping processes to optimize TFT performance
Data Source
AI summary
An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.