Array Substrate Protection Layer Height Variation
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Solution Overview
Problem
Peripheral data lines in array substrates are prone to scratching or crushing due to their relative fragility compared to peripheral gate lines, leading to line defects and instability in display performance.
Innovation Solution
The array substrate design features a protection layer with a surface height higher at peripheral gate line positions than at peripheral data line positions, with a groove for the data line to reduce contact with foreign materials, and a semiconductor layer overlapping the gate line to enhance protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the protection layer thickness is uniform across peripheral gate lines and peripheral data lines, then the manufacturing process is simple, but the peripheral data lines are more exposed and vulnerable to scratching or crushing by foreign materials
Solution Approach 1:
The patent applies local quality by creating different protection layer thicknesses at different locations. Specifically, the protection layer has a first thickness at peripheral gate line positions and a second thickness at peripheral data line positions, with the second thickness being greater than the first. This localized differentiation provides enhanced protection to the more vulnerable peripheral data lines while maintaining adequate protection for peripheral gate lines.
2Reliability
If the protection layer is made thicker to protect peripheral data lines, then the reliability improves, but the manufacturing complexity and cost increase
Solution Approach 1:
Rather than uniformly increasing the protection layer thickness across the entire substrate, the patent applies local quality by selectively increasing the thickness only at peripheral data line positions. This approach enhances reliability where needed while avoiding the unnecessary complexity and cost associated with a uniformly thick protection layer across all areas.
Data Source
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AI summary
The invention relates to the field of display design, and discloses an array substrate, a manufacturing method thereof, a display panel and a display device. The array substrate comprises a base substrate, and a peripheral gate line, a gate insulation layer, a peripheral data line and a protection layer which are formed on the base substrate in turn, wherein surface height of the protection layer corresponding to position where the peripheral gate line is located is higher than that of the protection layer corresponding to position where the peripheral data line is located. As such, when in contact with a peripheral wiring area of the array substrate, a foreign material is first in contact with the protection layer corresponding to position where the peripheral gate line is located, thereby reducing probability of crushing or scratching the peripheral data line by the foreign material, improving the stability of product performance.