Array Substrate Protection Layers for Chip on Film Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the chip on film package process, the exposure of source and drain metal in the PIN region leads to etching issues during the planarization process, causing aluminum peeling and increased contact resistance, resulting in defective display screens with a high defective rate.
Innovation Solution
The array substrate design includes a via hole in the interlayer dielectric layer with protection layers between the second electrode structure and the third electrode structure, using a half tone mask to cover the exposed side end faces, preventing etching and peeling of the metal layers, and ensuring better bonding with other film layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source and drain metal are exposed in the PIN region during the planarization process, then the etching process can proceed, but this causes aluminum peeling and increased contact resistance leading to defective display screens
Solution Approach 1:
The patent introduces a protection layer as an intermediary substance between the exposed metal and the etching environment. This protection layer prevents direct contact between the etching solution and the metal surfaces, thereby preventing aluminum peeling and contact resistance increase while still allowing the planarization process to proceed. The protection layer acts as a mediator that enables the manufacturing process without causing the harmful effects.
2Manufacturing precision
If the metal layers are exposed for etching, then the planarization can be achieved, but this leads to metal peeling and corrosion
Solution Approach 1:
The patent applies the preliminary action principle by forming the protection layer before the etching process begins. The protection layer is deposited on the exposed metal surfaces in advance, creating a protective barrier that prevents the subsequent etching process from causing metal peeling and corrosion. This preliminary protective measure ensures that the metal layers maintain their structural integrity throughout the planarization process.
Data Source
AI summary
Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.