Array Substrate PTC Thermistor Gate Line Routing
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Solution Overview
Problem
Large-scale liquid crystal display (LCD) panels face issues with increased wiring resistance in array substrates, leading to reduced pixel aperture ratio, increased power consumption, and display defects such as green casts, flashes, and afterimages.
Innovation Solution
The use of positive temperature coefficient (PTC) thermistors to connect common electrodes to gate lines, allowing for reduced wiring of common electrode lines and eliminating the need for common voltage input signals, thereby increasing pixel aperture ratio and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If common electrode lines are arranged in parallel with gate lines and connected via via holes to achieve conduction in the vertical direction, then the array substrate can be manufactured with conventional processes, but the wiring resistance increases and pixel aperture ratio is reduced
Solution Approach 1:
The patent merges the common electrode line routing with the gate line structure. Instead of separate common electrode lines requiring via holes for vertical conduction, the gate lines themselves serve as the conduction paths for common electrodes. This integration eliminates the need for additional via holes and reduces overall wiring resistance while maintaining manufacturability through conventional processes.
Solution Approach 2:
The gate lines are assigned multiple functions: they control the TFT switching function and simultaneously serve as conduction paths for the common electrodes. This multi-functionality reduces the need for separate common electrode lines and via holes, thereby reducing wiring resistance and increasing pixel aperture ratio.
2Ease of manufacture
If common electrode lines are arranged in parallel with gate lines and connected via via holes, then the array substrate can be manufactured with conventional processes, but the pixel aperture ratio is reduced
Solution Approach 1:
The patent merges the common electrode line routing with the gate line structure. Instead of separate common electrode lines requiring via holes for vertical conduction, the gate lines themselves serve as the conduction paths for common electrodes. This integration eliminates the need for additional via holes and reduces overall wiring resistance while maintaining manufacturability through conventional processes.
Solution Approach 2:
The patent extracts and eliminates the via hole structures from the conventional design. By removing the via holes that were previously necessary for vertical conduction of common electrodes, the pixel aperture area is increased while maintaining manufacturability through direct gate line conduction.
3Ease of manufacture
If conventional common electrode line wiring is used, then the array substrate can be manufactured with standard processes, but the power consumption increases
Solution Approach 1:
The patent merges the common electrode line routing with the gate line structure. Instead of separate common electrode lines requiring via holes for vertical conduction, the gate lines themselves serve as the conduction paths for common electrodes. This integration eliminates the need for additional via holes and reduces overall wiring resistance while maintaining manufacturability through conventional processes.
Solution Approach 2:
The gate lines act as an intermediary structure that simultaneously performs TFT control and common electrode conduction functions. This intermediary role reduces the need for separate conduction paths, thereby reducing overall wiring resistance and power consumption while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the display effect by increasing pixel aperture ratio and significantly reducing power consumption while avoiding display defects associated with high wiring resistance.
Implementation Method 1
positive temperature coefficient (PTC) thermistors configured to respectively connect the common electrode of each pixel unit to any one of gate lines arranged corresponding to any pixel row except the pixel row in which the pixel unit is disposed
Data Source
AI summary
Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a plurality of pixel units, a plurality of gate lines and positive temperature coefficient (PTC) thermistors. The pixel units are arranged in a matrix and include a plurality of pixel rows and a plurality of pixel columns. Each pixel unit includes a common electrode and a thin-film transistor (TFT). The gate lines are arranged corresponding to each pixel row respectively and connected to the TFT of each pixel unit of a corresponding pixel row respectively. The PTC thermistors are configured to respectively connect the common electrode of each pixel unit to any one of gate lines arranged corresponding to any pixel row except the pixel row in which the pixel unit is disposed.