Array Substrate Recess Structure for IPS Display Manufacturing
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Solution Overview
Problem
The existing manufacturing process for in-plane-switching (IPS) display panels is complex and has a low conformity rate, leading to increased size and reduced viewing angle due to the need for multiple etching steps to form horizontal electrode structures for liquid crystal molecules.
Innovation Solution
The formation of a recess by etching a first and second dielectric material layer, simplifying the manufacturing process and reducing the overall size by eliminating the need for multiple etching steps, while maintaining electrical connectivity between electrode layers through through holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple etching steps are used to form horizontal electrode structures, then the electrode connectivity is achieved, but the manufacturing complexity increases and conformity rate decreases
Solution Approach 1:
The patent combines multiple etching steps into a single etching process by forming a composite mask structure (first mask layer and second mask layer) that enables simultaneous creation of through holes in both first and second dielectric layers. This merging of operations reduces manufacturing complexity while maintaining electrode connectivity through the integrated recess structure.
2Reliability
If multiple etching steps are performed, then the electrode structure is formed, but the manufacturing time increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by forming the first mask layer and second mask layer in advance before the etching process. These pre-formed mask structures are specifically designed to enable simultaneous etching of multiple dielectric layers, thereby reducing the number of sequential steps required during the actual manufacturing process and improving overall productivity.
3Area of stationary object
If the array substrate size is reduced, then the display device becomes more compact, but the aperture rate may be affected
Solution Approach 1:
The patent utilizes vertical dimensionality by forming a recess structure that extends downward through multiple dielectric layers. This vertical space utilization allows the electrode structure to be compacted in the horizontal plane, reducing overall substrate area while maintaining sufficient aperture area for liquid crystal alignment, thus achieving both compactness and high aperture rate.
4Reliability
If through holes are formed in dielectric layers, then electrical connectivity is achieved, but the risk of electrostatic discharge increases
Solution Approach 1:
The patent introduces an intermediary protective layer (third dielectric layer or protective film) that covers the recess structure and through holes. This intermediary layer acts as a barrier against electrostatic discharge while allowing electrical connectivity to be maintained through the underlying through hole structure, thus protecting the device from harmful ESD effects.
Data Source
AI summary
An array substrate structure including a first substrate, a plurality of thin film transistors, a first dielectric layer, a second dielectric layer, and a second electrode layer is provided. Each of the thin film transistors has a patterned first electrode layer which is disposed on the first electrode layer and has a first through hole. The second dielectric layer is disposed on the first dielectric layer and has a second through hole. The second through hole is connected to the first through hole, such that the second electrode layer is electrically connected to the first electrode layer via the first through hole and the second through hole.