Array Substrate Peripheral Wiring for Narrow-Frame Rounded Corners
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Solution Overview
Problem
Existing OLED display panels face challenges in achieving a high screen ratio and aesthetic design with irregular rounded corners, which compromise the circuit arrangement in the peripheral region, leading to increased space occupation and reduced display effectiveness.
Innovation Solution
The array substrate design incorporates multi-layer wiring for connection portions and selection switches, allowing for a narrow frame and irregular edge design by alternating arrangements of connection portions and selection switches, reducing space occupation while maintaining effective signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the circuit pattern is arranged in the peripheral region with irregular rounded corners to improve display aesthetics and narrow frame, then the screen ratio is improved, but the circuit arrangement space is reduced and circuit layout becomes more difficult
Solution Approach 1:
The circuit pattern is divided into multiple segments including data lead lines, selection switches, and connection portions arranged in different regions. The peripheral region is segmented into first peripheral regions for data lead lines and second peripheral regions for selection switches, allowing independent optimization of each segment's layout to fit irregular shapes while maintaining functionality
Solution Approach 2:
The circuit layout transitions from traditional planar arrangement to multi-dimensional spatial utilization by arranging components along irregular curved edges and utilizing corner regions. Connection portions extend along curved edges between selection switches, effectively using the two-dimensional peripheral space in non-linear configurations to accommodate rounded corner designs
2Length of stationary object
If the frame is narrowed and irregular edges are designed to improve aesthetics, then the screen ratio is improved, but the space for circuit arrangement is reduced
Solution Approach 1:
Different regions of the peripheral circuit are designed with locally optimized layouts: data lead lines are arranged in first peripheral regions with specific spacing, while selection switches are placed in second peripheral regions. Connection portions are designed to extend along curved edges between switches, with each local area optimized for its specific function while collectively fitting within the narrowed frame
Solution Approach 2:
The circuit layout adapts dynamically to the irregular shape by allowing connection portions to follow curved edges and by positioning selection switches at strategic locations along the perimeter. The arrangement flexes to accommodate the rounded corner geometry rather than maintaining rigid straight-line configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a narrow frame and improved display aesthetics by optimizing circuit layout in the peripheral region, ensuring uniform power supply and signal transmission, even in irregularly shaped display regions.
Implementation Method 1
a photosensitive resin layer is provided on the transparent substrate
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
An array substrate and a display panel are disclosed. The array substrate includes: a base substrate (01) including a display region (AA) and a peripheral region (BB); a plurality of sub-pixels (02) in the display region (AA); a plurality of data lines (03) in the display region (AA); a plurality of first power lines (04) in the display region (AA); a plurality of data lead lines (05) in the peripheral region (BB); a plurality of selection switches (06) in the peripheral region (BB); a plurality of data signal input lines (07) in the peripheral region (BB); a first power bus (08) in the peripheral region (BB); and a plurality of connection portions (09) electrically connecting the first power bus (08) to the plurality of first power lines (04), respectively. The plurality of connection portions (09) include a plurality of first connection portions (09A) and a plurality of second connection portions (09B) on both sides of the plurality of first connection portions (09A). The above circuit arrangement is beneficial to the circuit arrangement in the corner region of the array substrate, thereby achieving narrow frame design.