Array Substrate SDT Etching Process for Active Layer Wing Reduction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The conventional 4-mask process for manufacturing TFT-LCD array substrates is complex and time-consuming, leading to uneven etching, active layer wings that degrade product quality, and increased processing time.

Innovation Solution

A modified SDT etching process that involves forming a gate signal line and gate electrode, simultaneously etching the active layer and ashing the photoresist to expose the metal layer, removing the metal layer within the channel region, and depositing a passivation layer with a via hole for connecting the pixel electrode to the drain electrode, reducing the active layer wing and processing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional 4-mask process with multiple sequential etching steps is used, then the active layer pattern can be formed, but the processing time is excessive and active layer wings are generated that degrade product quality

Engineering Contradiction:

Improveactive layer pattern precisionVSAvoidprocessing time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines multiple sequential etching steps into a single simultaneous etching process. The photoresist pattern serves as a mask while etching both the metal layer and active layer at the same time, eliminating the need for separate etching steps and reducing processing time by 40-70 seconds per substrate.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary ashing of the photoresist during the etching process itself, rather than as a separate preparatory step. This allows the photoresist to be removed in-situ, exposing the metal layer within the channel region and enabling subsequent metal layer etching without additional processing steps.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If multiple sequential etching processes are performed, then the metal layer and active layer can be patterned, but uneven etching occurs causing embossing mura that affects product quality

Engineering Contradiction:

Improvepattern uniformityVSAvoidembossing mura

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent combines metal layer etching and active layer etching into a single simultaneous process using the same photoresist mask. This ensures uniform etching conditions and prevents the uneven etching that occurs when separate etching steps are performed with different parameters, thereby eliminating embossing mura defects.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If the photoresist is not ashed before metal layer etching, then additional processing steps are required, but the metal layer within the channel region cannot be exposed for proper source/drain electrode formation

Engineering Contradiction:

Improveprocess simplicityVSAvoidsource/drain electrode formation precision

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The SDT etching process reduces processing time by 40-70 seconds, minimizes active layer wing width, enhances design and product quality, and avoids unevenness, improving yield and aperture ratio.

Implementation Method 1

removing the metal layer outside a region for forming a data line, a channel and source/drain electrodes with the photoresist pattern as an etching mask

Methodology Applied

Scientific EffectWet etching:

Implementation Method 2

ashing the photoresist so as to expose the metal layer within a channel region

Methodology Applied

Scientific EffectAashing:

Implementation Method 3

removing the metal layer within the channel region by performing a wet etch or a dry etch

Methodology Applied

Scientific EffectWet etching:

Implementation Method 4

removing the metal layer within the channel region by performing a wet etch or a dry etch

Methodology Applied

Scientific EffectDry etching:

Implementation Method 5

removing a part of the active layer within the channel region so as to form the channel

Methodology Applied

Scientific EffectEtching:

Implementation Method 6

depositing a passivation layer on the base substrate

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 7

depositing a passivation layer on the base substrate

Methodology Applied

Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 8

depositing a transparent pixel electrode layer

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS9190429B2Manufacturing method of array substrate

Publication Date: 2015.11.17 BOE TECHNOLOGY GROUP CO LTD

AI summary

A manufacturing method of an array substrate, comprising the following steps: S1 forming a gate signal line and a gate electrode on a base substrate, successively depositing a gate insulating layer, an active layer, and a metal layer, faulting a mask formed of photoresist on the metal layer, and removing the metal layer outside a region for forming a data line and source/drain electrodes through the mask; S2. simultaneously etching the active layer and ashing the photoresist so as to expose the metal layer within a channel region; S3. etching the active layer exposed by the photoresist after being ashed after the step S2; S4. removing the metal layer within the channel region.