Array Substrate Layout for Seamless Spliced Display Panels
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Solution Overview
Problem
Conventional spliced display panels, including LCD, OLED, Mini-LED, and Micro-LED, face challenges in achieving seamless splicing due to virtual seams from panel splicing and limitations in mass transfer technology, leading to unsatisfactory screen size and bezel width.
Innovation Solution
An array substrate design with modularly arranged pixel driving sub-circuits and functional sub-circuits, centralized shift register circuits, and fan-out structures on a dual-surface base, enabling efficient space utilization and seamless splicing by reducing or eliminating the bezel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional splicing methods are used to achieve larger screen size, then the display area can be expanded, but virtual seams and bezel width increase
Solution Approach 1:
The array substrate is divided into multiple independently controllable pixel groups, each with its own pixel circuit groups and shift register circuits. This segmentation allows multiple substrates to be spliced together while maintaining uniform control and reducing visible seams through precise alignment and matching of adjacent segments.
Solution Approach 2:
Pixel circuit groups are arranged in the first direction between pixel lines, and shift register circuits are positioned between pixel groups, utilizing spatial dimensions efficiently. This multi-dimensional arrangement optimizes space utilization and enables seamless splicing by distributing control functions across different spatial layers.
2Reliability
If pixel circuits are distributed throughout the display area, then signal control is improved, but space utilization decreases
Solution Approach 1:
The display area is segmented into pixel groups with dedicated pixel circuit groups positioned between pixel lines. This segmentation concentrates control functions in specific regions rather than distributing them throughout the entire display area, improving space utilization while maintaining effective signal control through localized circuit groups.
Solution Approach 2:
Multiple pixel circuit groups are merged into compact arrangements between adjacent pixel lines, and shift register circuits are combined and positioned strategically between pixel groups. This merging reduces the total area occupied by control circuits while maintaining comprehensive signal control over the display area.
3Reliability
If more functional circuits are added to improve display performance, then display quality improves, but device complexity increases
Solution Approach 1:
Pixel circuit groups are designed as multi-functional units that can perform multiple display control functions. Each pixel circuit group includes transistors and capacitors that can handle different signal types and control modes, reducing the need for separate dedicated circuits for each function and thereby simplifying the overall device complexity.
Solution Approach 2:
Functional circuits are segmented into modular pixel circuit groups that can be independently designed and optimized. This modularity allows complex functions to be broken down into manageable units, making the overall system easier to control and maintain while improving display performance through targeted functional enhancements.
Data Source
AI summary
An array substrate has a display area, and includes a base, pixel groups arranged in multiple lines in a first direction, pixel circuit groups arranged in the first direction, and at least one shift register circuit. Each of at least one pixel group includes a plurality of pixels arranged in at least one line. Each pixel includes at least one sub-pixel. Each of at least one pixel circuit group is disposed between two adjacent lines of pixels, each pixel circuit group includes a pixel driving sub-circuit group, and the pixel driving sub-circuit group is configured to supply pixel driving signals to sub-pixels electrically connected to the pixel driving sub-circuit group. A shift register circuit is disposed between two adjacent lines of pixels, and the shift register circuit is configured to supply scan driving signals to at least one pixel driving sub-circuit group electrically connected to the shift register circuit.