Array Substrate Manufacturing with Segmented Protective Layers
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Solution Overview
Problem
The existing manufacturing process of array substrates for TFT-LCD displays using a back channel etching structure results in poor interface status leading to large TFT electric leakage and residual image issues due to excessive semiconductor active layer width and doped silicon tail phenomena.
Innovation Solution
A method involving sequential deposition and patterning of metal and insulating layers using halftone and photomasks to form a semiconductor active layer with a width less than the gate metal layer, incorporating a channel protective layer and via holes to reduce the semiconductor active layer width and alleviate doped silicon tail issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a back channel protective layer etching (BCE) structure is used, then structure costs are reduced and manufacturing process is simplified, but TFT electric leakage increases due to poor interface status
Solution Approach 1:
The invention divides the protective layer into two distinct parts: a first protective layer covering the active layer during etching, and a second protective layer (back channel protective layer) covering the channel region. This segmentation allows each layer to perform its specific function independently, protecting the interface while enabling the BCE structure's manufacturing advantages.
Solution Approach 2:
The first protective layer is formed before the BCE etching process to pre-protect the active layer interface. This preliminary protective action ensures that the interface status is maintained during subsequent etching operations, preventing the electric leakage issues that would otherwise occur with BCE structures.
2Productivity
If 4-mask technology is used to combine gate insulating layer with second metal layer, then manufacturing steps are reduced, but semiconductor active layer width becomes excessively large causing doped silicon tail and image sticking issues
Solution Approach 1:
The invention separates the formation of the gate insulating layer and the second metal layer into distinct masking steps. Instead of combining them in a single 4-mask process, the gate insulating layer is formed in an earlier step, and the second metal layer is formed later with precise width control, preventing the active layer width from becoming excessively large.
Solution Approach 2:
The gate insulating layer is formed in advance before the second metal layer deposition. This preliminary formation allows for independent optimization of each layer's dimensions, ensuring that the semiconductor active layer width is precisely controlled to prevent doped silicon tail formation while still maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the semiconductor active layer width, improving the interface status, minimizing TFT electric leakage, and alleviating residual image impacts, thereby enhancing the endurance of the display panel.
Implementation Method 1
performing exposure once above the semiconductor active base layer by using a halftone photomask, and forming a gate metal layer, a gate insulating layer, and a semiconductor active layer above the semiconductor active base layer
Implementation Method 2
coating a photoresist material layer on the second passivation base layer, performing patterning treatment on a photoresist material by using the second photomask
Implementation Method 3
etching the second metal base layer by wet etching once by using the formed pattern of the second passivation layer as a protective layer, so that the second metal base layer breaks into the source metal layer and the drain metal layer
Data Source
AI summary
This application provides a method for manufacturing an array substrate, an array substrate, and a display panel. A gate metal layer, a gate insulating layer, and a semiconductor active layer are formed by using one photomask process, a first passivation layer is formed in one photomask process, and a source metal layer, a drain metal layer, and a pixel electrode layer are formed on the first passivation layer.