Array Substrate Shared Connection Portion for Transistor Interconnect
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Solution Overview
Problem
The complexity of the circuit structure in active matrix displays, which includes multiple thin film transistors, poses a challenge in simplifying the design and reducing circuit space, particularly in connecting active layers of different transistors without occupying additional area.
Innovation Solution
The array substrate design incorporates a first and second active layer of thin film transistors with a shared connection portion that overlaps source or drain contact regions, allowing electrical connection through a via in the insulating layer, thereby eliminating the need for additional space-consuming vias and bridges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate vias and bridges are used to connect active layers of different transistors, then electrical connectivity is achieved, but circuit space increases and device complexity increases
Solution Approach 1:
The patent merges the connection portion with the source or drain electrode of the second thin film transistor. The connection portion and the source/drain electrode are formed in the same metal layer and share the same structural form, eliminating the need for separate via and bridge structures. This combining approach achieves electrical connectivity between the first and second active layers while reducing circuit space occupation.
Solution Approach 2:
The connection portion serves multiple functions: it acts as both the electrical connector between different active layers and as the source or drain electrode of the second thin film transistor. This multi-functionality reduces the number of separate components needed, thereby simplifying the circuit structure and reducing the area occupied by connection elements.
2Reliability
If additional via and bridge structures are added for transistor connection, then electrical connectivity is ensured, but manufacturing complexity increases
Solution Approach 1:
The patent combines the connection portion with the source/drain electrode structure, forming a unified component rather than separate via and bridge elements. This merging simplifies the circuit structure by reducing the number of discrete components and their corresponding fabrication steps, thereby lowering manufacturing complexity while maintaining electrical connectivity.
3Area of stationary object
If overlapping connection structure is used, then circuit space is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The connection portion is merged with the source/drain electrode and formed through the same patterning process. This integration means that the alignment requirements are governed by the existing source/drain electrode fabrication precision rather than requiring additional high-precision alignment steps, thereby reducing the overall manufacturing precision burden while achieving space reduction.
Data Source
AI summary
Provided are an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: a substrate, a first active layer of a first thin film transistor, a first insulating layer, a first metal layer, and a second active layer of a second thin film transistor. The first metal layer includes a first connection portion, which overlaps one of a source contact region or a drain contact region of the first active layer and overlaps one of a source contact region or a drain contact region of the second active layer. The one of the source contact region or the drain contact region of the first active layer and the one of the source contact region or the drain contact region of the second active layer overlap each other, and are electrically connected through a via in the first insulating layer and the first connection portion.