Array Substrate Layout With Shared ITO Wiring for Higher Aperture
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Solution Overview
Problem
The existing 8-domain pixel structure in large-sized liquid crystal displays has a low aperture ratio due to the arrangement of opaque metal drains from shared transistors that penetrate the main and sub-pixel areas, limiting light transmittance and image quality.
Innovation Solution
An array substrate design featuring shared metal wiring made of indium tin oxide, which is electrically connected to the source of shared transistor units, reducing the need for opaque metal drains to penetrate the pixel area, and arranging the main and sub-pixel areas on the same side of the transistor area to minimize coupling capacitance and increase aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If opaque metal drains from shared transistors are arranged in tandem and penetrate the main and sub-pixel areas, then the transistor structure is simplified and manufacturing is easier, but the aperture ratio and light transmittance are reduced
Solution Approach 1:
The patent moves the shared transistor drains from the pixel area to the peripheral region, and introduces shared metal wiring that extends in the row direction above the transistor area. This dimensional reorganization allows the drains to be positioned outside the pixel area while maintaining electrical connection through the shared metal wiring, thereby resolving the contradiction between manufacturing simplicity and aperture ratio.
Solution Approach 2:
The shared metal wiring acts as an intermediary element that connects the shared transistor drains (positioned in the peripheral region) to the pixel circuits. This intermediary structure enables the drains to be located outside the pixel area while still providing the necessary electrical connections, thus increasing the aperture ratio without complicating the transistor structure.
2Reliability
If opaque metal drains penetrate the pixel area to connect shared transistor units, then electrical connection is achieved, but light transmittance and image quality are degraded
Solution Approach 1:
The patent extracts the shared transistor drains from the pixel area and relocates them to the peripheral region. By taking out the opaque metal drains from the light-transmitting pixel area, the patent maintains electrical connection functionality while significantly improving light transmittance and image quality.
Solution Approach 2:
The shared metal wiring extends in the row direction above the transistor area, creating a three-dimensional routing path that allows electrical connections to be made without requiring opaque drains to penetrate the pixel area. This dimensional change separates the electrical connection function from the light transmittance function in space.
3Area of stationary object
If the sub-pixel electrode of the main pixel area overlaps the data line to shield the electric field, then coupling capacitance is reduced and aperture ratio is increased, but the structure becomes more complex
Solution Approach 1:
The patent merges the function of the sub-pixel electrode with the data line shielding function. By designing the sub-pixel electrode to extend and overlap the data line, the patent simultaneously achieves the capacitance shielding effect and maintains a relatively simple overall structure, avoiding the need for additional separate shielding elements.
Data Source
AI summary
The prevent application provides an array substrate and a display panel. The array substrate is provided with a plurality of rows of pixel units, wherein each of the pixel units is provided with a transistor area; a main transistor unit, a sub-transistor unit, and a shared transistor unit are disposed in the transistor area; and the shared transistor unit includes a source and a drain; each of the plurality of rows of the pixel units is provided with a shared metal wiring; and the shared metal wiring is provided above the transistor area and extends along an arrangement direction of the pixel units in a corresponding one of the plurality of rows, and is electrically connected to a source of the shared transistor unit in each of the pixel units, sequentially.