Array Substrate Layout With Shared Masking for TFT Electrodes
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Solution Overview
Problem
The existing fabrication processes for array substrates in display devices require multiple masking steps, leading to a complex and inefficient process due to the need for separate masking for light shielding, source/drain, and gate layers, which complicates the manufacturing of display panels.
Innovation Solution
The array substrate design and fabrication method involve a primary masking process for forming a first metal layer with a light shielding part, source, and drain, and a second metal layer with a gate, source landing electrode, and drain landing electrode, where the via holes expose the active layer ends, allowing simultaneous contact and reducing the number of masking steps required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masking steps are used for light shielding, source/drain, and gate layers, then each layer can be formed with precise control, but the fabrication process becomes complex and inefficient
Solution Approach 1:
The patent combines the formation of light shielding layer, source/drain electrodes, and gate electrode into a single masking step. The pixel electrode, auxiliary electrode, and signal line are patterned simultaneously using one mask, eliminating the need for separate masking steps for each layer, thus simplifying the fabrication process while maintaining manufacturing precision
Solution Approach 2:
The single masking step serves multiple functions: it defines the light shielding layer, source/drain electrodes, gate electrode, pixel electrode, auxiliary electrode, and signal lines all in one operation. This multi-functional approach reduces process complexity while ensuring consistent alignment and precision across all components
2Manufacturing precision
If multiple masking steps are used for forming different layers, then each component can be precisely positioned, but the manufacturing efficiency decreases
Solution Approach 1:
The patent merges multiple positioning operations into a single masking step where all electrodes and conductive structures are patterned simultaneously. This maintains precise positioning through careful mask design while dramatically improving manufacturing efficiency by reducing the number of sequential steps required
3Ease of manufacture
If separate masking processes are used for light shielding and source/drain formation, then each layer can be optimized independently, but the overall process time increases
Solution Approach 1:
The patent combines the optimization of light shielding layer and source/drain electrodes into a single masking process. The mask is designed to simultaneously define both structures with their respective optimal geometries, maintaining design flexibility while reducing total process time by eliminating sequential operations
Data Source
AI summary
An array substrate, a display device and a fabrication method are provided. The array substrate includes a first metal layer at one side of a base substrate, the first metal layer including a light shielding part, a source, a drain in a display area; a second metal layer at a side, facing away from an active layer, of gate insulating layer, the second metal layer includes a gate, a source-landing electrode a drain-landing electrode in the display area, the source-landing electrode is in contact with the active layer and the source through a first via hole penetrating through the gate insulating layer and a buffer layer and exposing one end of the active layer, the drain-landing electrode is in contact with the active layer and the drain through a second via hole penetrating through the gate insulating layer and the buffer layer and exposing other end of the active layer.