Array Substrate Clock-Line Testing With Shared Terminals
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Solution Overview
Problem
The existing array substrate testing methods require a large number of testing terminals and pins, which increases production costs and device volume due to the need for each clock signal line to be connected to a separate testing terminal, limiting the number of clock signal lines that can be effectively tested.
Innovation Solution
The array substrate design includes a configuration where multiple clock signal lines are connected to a fewer number of testing terminals, with at least two clock signal lines connected to the same testing terminal, reducing the overall number of testing terminals and pins required, while maintaining effective signal transmission and testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each clock signal line is connected to a separate testing terminal, then the testing accuracy and reliability are improved, but the number of testing terminals and pins increases, leading to increased production costs and device volume
Solution Approach 1:
Multiple clock signal lines are merged to share a common testing terminal. Specifically, the patent connects multiple clock signal lines (CLK1, CLK2, CLK3, CLK4) to a single testing terminal through a testing controller that can selectively activate different clock lines during testing, thereby reducing the total number of testing terminals required while maintaining comprehensive testing coverage
Solution Approach 2:
The testing terminal is designed with multi-functionality to serve multiple clock signal lines. The testing controller can configure the single testing terminal to test different clock signal lines at different time intervals, making the testing terminal universal and adaptable to various testing scenarios without requiring dedicated terminals for each clock line
2Device complexity
If the number of testing terminals is reduced, then production costs and device volume are decreased, but the number of clock signal lines that can be effectively tested is limited
Solution Approach 1:
The testing system employs periodic action by sequentially activating different clock signal lines through the shared testing terminal over time. The testing controller implements time-multiplexed testing where each clock line is tested in alternating time slots, ensuring that all clock lines are comprehensively tested despite sharing a single terminal, thus maintaining high testing productivity
Solution Approach 2:
The testing system is designed to be dynamic and reconfigurable. The testing controller can dynamically allocate the shared testing terminal to different clock signal lines based on testing requirements, enabling flexible adaptation to various testing scenarios and ensuring optimal testing efficiency without being constrained by a fixed one-to-one terminal-to-line mapping
3Device complexity
If multiple clock signal lines are connected to the same testing terminal, then the number of pins is reduced, but signal interference and crosstalk may increase
Solution Approach 1:
The system performs preliminary actions by pre-configuring the testing terminal and controlling the activation timing of different clock signal lines before actual testing begins. The testing controller establishes proper signal isolation and timing sequences in advance, preventing signal interference and crosstalk from occurring during the testing process
Solution Approach 2:
The testing controller serves as an intermediary between the shared testing terminal and multiple clock signal lines. It manages signal routing, timing, and isolation, acting as a mediator that prevents direct signal interference between clock lines while still allowing them to share the common terminal through controlled, sequential access
Data Source
AI summary
An array substrate and a testing method thereof are provided. The array substrate includes a gate driving circuit, a plurality of clock signal lines and a plurality of testing terminals, wherein a number of the clock signal lines is greater than a number of the testing terminals; the plurality of clock signal lines are connected to the gate driving circuit and the plurality of testing terminals, and at least two clock signal lines are connected to a same testing terminal; and the plurality of testing terminals are configured to connect to a testing device.