Array Substrate Shielding for Vertical Line Elimination
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Solution Overview
Problem
The dual gate pixel structure in TFT-LCDs leads to pixel voltage fluctuations due to gate voltage jumps, resulting in differences in brightness across columns of pixels and the appearance of vertical lines when the display is viewed from different angles.
Innovation Solution
The array substrate design includes sub-pixel regions with two sub-pixel units connected to thin film transistors via connecting portions of different lengths, and a common electrode layer with a shielding portion located above the longer connecting portion and/or the gate line connected to the thin film transistor, reducing capacitance between the connecting portions and the gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If connecting portions of different lengths are used to connect sub-pixel units to thin film transistors, then the dual gate pixel structure can be implemented to reduce Source IC quantity, but pixel voltage fluctuation occurs due to capacitance differences causing brightness differences and vertical lines
Solution Approach 1:
The patent introduces a shielding portion in the common electrode layer specifically positioned above the longer connecting portion to reduce its capacitance with the gate line. This local modification creates different shielding effects for different connecting portions, compensating for the capacitance difference caused by their length difference, thereby stabilizing pixel voltage while maintaining the dual gate pixel structure
Solution Approach 2:
The shielding portion acts as an intermediary element between the longer connecting portion and the gate line. By introducing this intermediate structure, the patent reduces the harmful capacitance coupling between the connecting portion and gate line, thereby mitigating the voltage fluctuation problem while preserving the benefits of the dual gate pixel structure
2Reliability
If the common electrode layer includes a shielding portion above the longer connecting portion, then capacitance between the connecting portion and gate line is reduced, but the device structure becomes more complex
Solution Approach 1:
The shielding portion is formed as an integral part of the common electrode layer, allowing it to simultaneously serve as both the common electrode and the shielding structure. This multi-functional design reduces the need for additional separate shielding components, thereby stabilizing pixel voltage while minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces voltage variations caused by connecting portions of different lengths, effectively eliminating the phenomenon of vertical lines in the display screen by minimizing capacitance and stabilizing pixel voltage.
Implementation Method 1
reduces capacitance between the connecting portions and the gate lines
Implementation Method 2
a common electrode layer, including an electrode line body and a shielding portion connected to the electrode line body, wherein the shielding portion is located above the first connecting portion and/or the shielding portion is located above the gate line connected to the thin film transistor corresponding to the first connecting portion
Data Source
AI summary
The present disclosure relates to an array substrate, a display panel, and an electronic device. The array substrate includes a plurality of sub-pixel regions, a gate line layer, and a common electrode layer. Each sub-pixel region of the sub-pixel regions has two sub-pixel units disposed in a same row and two thin film transistors connected to the two sub-pixel units respectively. The gate line layer has gate lines and gate electrodes. Control electrodes of two thin film transistors of each sub-pixel region are respectively connected to two gate lines located on two ends of the sub-pixel region through corresponding gate electrodes.