Array Substrate Line Overlap Layout for Lower Signal Delay
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Solution Overview
Problem
The increase in line thickness in array substrates of liquid crystal display devices leads to an increase in cross-sectional area, resulting in decreased resistance value and time constant, which causes signal delay.
Innovation Solution
The array substrate design includes a gate line, a source line, a switching component, a semiconductor film, and insulating films that overlap to reduce parasitic capacitance by increasing the distance between the gate and source lines, with the source line connected via a source electrode and drain electrode disposed between insulating films, thereby reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of lines is increased to decrease resistance value, then the resistance value is decreased and time constant is decreased, but the cross-sectional area increases and parasitic capacitance increases causing signal delay
Solution Approach 1:
The patent introduces a third dimension (vertical stacking) by disposing the gate line and source line in different layers that overlap each other. This spatial reconfiguration allows the lines to cross without increasing the cross-sectional area of individual lines, thereby maintaining low resistance while reducing parasitic capacitance through controlled overlap geometry.
Solution Approach 2:
The patent introduces an insulating film as an intermediary between the gate line and source line at their overlap region. This insulating film acts as a mediator that electrically isolates the two conductive lines, preventing direct capacitive coupling and thereby reducing parasitic capacitance while allowing the lines to maintain their low-resistance path.
2Reliability
If the line thickness is increased to reduce resistance, then the resistance value decreases, but the cross-sectional area increases leading to increased parasitic capacitance
Solution Approach 1:
The patent introduces a third dimension (vertical stacking) by disposing the gate line and source line in different layers that overlap each other. This spatial reconfiguration allows the lines to cross without increasing the cross-sectional area of individual lines, thereby maintaining low resistance while reducing parasitic capacitance through controlled overlap geometry.
Solution Approach 2:
The patent introduces an insulating film as an intermediary between the gate line and source line at their overlap region. This insulating film acts as a mediator that electrically isolates the two conductive lines, preventing direct capacitive coupling and thereby reducing parasitic capacitance while allowing the lines to maintain their low-resistance path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced parasitic capacitance decreases the time constant, minimizing signal delay and enabling higher refresh rates and increased pixel resolution in the liquid crystal panel.
Implementation Method 1
decrease of the parasitic capacitance of the transmission circuit may effectively suppress the signal delay rather than the decrease of the resistance value of the transmission circuit
Data Source
AI summary
An array substrate includes a gate line, a source line crossing the gate line, a switching component disposed on a crossing portion of the gate line and the source line, a semiconductor film included in the switching component, a first insulating film disposed between a layer including the gate line and a layer including the semiconductor film, and a second insulating film disposed between a layer including the semiconductor film and a layer including the source line. The source line overlaps the gate line via the first insulating film and the second insulating film.