Array Substrate Signal Isolation for Narrow Frame Displays

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Solution Overview

Problem

Existing display technologies face issues with signal interference between gate electrode driving signals and data driving signals in liquid crystal display panels, leading to abnormal pixel unit displays due to the close proximity of lead wires and data lines, which affects the transmittance and brightness of pixel units.

Innovation Solution

The solution involves arranging pixel units such that each pixel row is connected to data lines far away from the corresponding lead wires, with additional data lines placed on the sides of the array substrate to prevent signal interference, and a driving method that ensures scanning signals are input to lead wires while data signals are transmitted through data lines not adjacent to them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the gate electrode driving circuit is disposed on the top side of the array substrate and connected to gate electrode lines via vertical lead wires, then the width of left and right borders is reduced and narrow frame design is realized, but signal interference occurs between lead wires and data lines causing abnormal pixel unit display

Engineering Contradiction:
Improvewidth of borderVSAvoiddisplay normality
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent extracts the problematic interaction between lead wires and data lines by implementing a timing separation mechanism. The gate electrode driving circuit controls the timing of scanning signals to lead wires and data signals to data lines, effectively separating their operational time windows and eliminating mutual interference while maintaining the narrow border design.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies dynamic timing control where the gate electrode driving circuit dynamically adjusts the timing of signal transmission to lead wires based on the scanning row. By making the timing dynamic and adaptive to the current scanning state, the system avoids fixed interference patterns and ensures reliable pixel display throughout the entire scanning process.

Inventive Principle:
Principle #15Dynamics

2Illumination intensity

If lead wires and data lines are disposed in the same gap between adjacent pixel units, then the transmittance of pixel units is maintained, but mutual interference between scanning signals and data driving signals occurs

Engineering Contradiction:
ImprovetransmittanceVSAvoidsignal interference
Core Design Contradiction:
Illumination intensityVSObject-affected harmful factors

Solution Approach 1:

The patent implements periodic action by organizing signal transmission in distinct time periods corresponding to different scanning rows. During each scanning period, the gate electrode driving circuit activates specific lead wires while controlling data lines to remain inactive or transmit at different phases, creating a periodic pattern of signal transmission that prevents continuous interference and maintains both transmittance and signal integrity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9971218B2Display device, display panel, array substrate and driving method thereof
Publication Date: 2018.05.15 XIAMEN TIANMA MICRO ELECTRONICS
  • US9971218B2 patent drawing
  • US9971218B2 patent drawing
  • US9971218B2 patent drawing

AI summary

A display device, a display panel, an array substrate and a driving method thereof are provided. The array substrate includes a plurality of pixel units arranged in an array, m number of gate electrode lines extending along a first direction, a plurality of data lines and m number of lead wires extending along a second direction. The plurality of pixel units are arranged in pixel columns along the second direction and m number of pixel rows along the first direction. Each pixel column is disposed between two adjacent data lines. Pixel units in an ith pixel row are connected to an ith gate electrode line, and the ith gate electrode line is connected to an ith lead wire, where i is a positive integer and 1≤i≤m. The pixel units in the ith pixel row are connected to different data lines far away from the ith lead wire, respectively.