Array Substrate Mask Process Reduction via Signal Line Merging
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Solution Overview
Problem
The complex manufacturing process of array substrates for TFT LCDs requires multiple masks, leading to increased manufacturing time and cost due to the intricate structure and lengthy etching processes.
Innovation Solution
A method that reduces the number of mask processes by forming a first signal line with two sections on either side of a second signal line, using three masks to etch a conductive layer, an intermediate layer, and a conductive electrode, thereby simplifying the formation of connecting bridges and pixel electrodes, and forming capacitance isolation structures to reduce the number of separate mask processes needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing process with multiple masks is used to form the array substrate structure, then the manufacturing precision and reliability are improved, but the manufacturing time and cost increase
Solution Approach 1:
The patent merges the formation of the first signal line and second signal line into a single mask process. The conductive layer is patterned using one mask to simultaneously create both signal lines, eliminating the need for separate mask processes that were previously required. This consolidation reduces manufacturing time while maintaining the required etching precision through careful mask design and single-step etching parameters optimization.
2Productivity
If the number of masks is reduced to shorten manufacturing process, then manufacturing time and cost are reduced, but the complexity of each mask process increases
Solution Approach 1:
The patent segments the conductive layer into different functional regions (first signal line, second signal line, and connecting portions) within a single mask pattern. By designing the mask to include distinct pattern regions for each signal line and their connections, the complex routing is achieved through one etching step rather than multiple simpler steps. This segmentation approach maintains manufacturing efficiency while managing complexity through careful mask design.
Solution Approach 2:
The patent resolves signal line crossings by transitioning from a planar two-dimensional layout to a three-dimensional structure with vertical layers. The first and second signal lines are formed at different vertical levels or through overlapping patterns in the mask design, allowing them to cross without interference. This dimensional approach simplifies the mask process by eliminating the need for additional masks to handle complex crossings.
3Reliability
If five or four masks are used for etching process, then the array substrate structure is formed with high reliability, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple etching operations into a single mask process. By designing the mask to define all necessary patterns for the first signal line, second signal line, and their connections in one step, the number of masks is reduced from four or five to one or two. This merging maintains structure reliability through consistent etching parameters and single-step patterning while significantly reducing manufacturing cost by eliminating multiple mask alignment and etching cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the manufacturing time and cost by allowing the first signal line and second signal line to be formed in one mask process, saving on the number of mask processes and enhancing the efficiency of the array substrate manufacturing process.
Implementation Method 1
depositing a conductive layer on a substrate
Implementation Method 2
depositing an intermediate layer in sequence
Implementation Method 3
depositing a conductive electrode
Implementation Method 4
adopting HF to etch edges of the passivation layer and the insulation layer of the second connecting bridge
Data Source
AI summary
The present disclosure relates to an array substrate and the manufacturing method thereof. The manufacturing method includes depositing a conductive layer on a substrate, forming three poles of at least one thin film transistor (TFT), a first signal line, and a second signal line by etching the conductive layer via a first mask, The method also includes depositing an intermediate layer in sequence, forming a first connecting bridge connecting a first portion and a second portion by etching the intermediate layer via a second mask, depositing a conductive electrode, and forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask. In this way, the time of the manufacturing process of the array substrates may be reduced such that the manufacturing cost may be decreased.