Array Substrate Wire Layout to Prevent Mini-LED Signal Overlap
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Solution Overview
Problem
Conventional technologies face issues with overlapping signal lines electrically connected to driver chips in Mini-LED display panels, leading to layout disadvantages and increased complexity.
Innovation Solution
The solution involves a substrate with specific bonding regions, conductive pads, and wires arranged such that second conductive pads connected to a second wire are located on the same side of first wires, avoiding overlaps and simplifying the layout by reducing the number of metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal lines are arranged to connect driver chips in conventional Mini-LED displays, then electrical connectivity is achieved, but signal line overlaps occur causing layout complexity and potential shorting risks
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar 2D layout to a 3D stacked architecture. Driver chips are positioned at different vertical levels (first bonding region and second bonding region) on the substrate, allowing signal lines to be routed in separate vertical planes. This eliminates overlaps and shorting risks while maintaining all necessary electrical connections, directly resolving the layout complexity issue.
2Reliability
If multiple metal layers are used to avoid signal line overlaps, then shorting risks are reduced, but manufacturing complexity and costs increase
Solution Approach 1:
Instead of adding more metal layers in the horizontal plane, the patent utilizes the vertical dimension by placing driver chips at different bonding regions (first and second bonding regions) on the substrate. This allows signal lines to be routed in separate vertical planes using the same metal layers, preventing shorting without increasing manufacturing complexity or requiring additional metal deposition processes.
3Manufacturing precision
If driver chips are densely packed to improve display resolution, then pixel density increases, but signal line routing becomes more complex and overlaps increase
Solution Approach 1:
The patent resolves signal line routing complexity by distributing driver chips across multiple vertical levels (first bonding region and second bonding region). This vertical separation allows signal lines to be routed independently in different planes, eliminating overlaps even when driver chips are densely packed horizontally. The approach maintains high pixel density while simplifying signal line routing through spatial separation in the vertical dimension.
Data Source
AI summary
The present invention provides an array substrate, a backlight module, and a display panel, by locating two second conductive pads connected to a second wire on the same side of a first wire, the present invention prevents an overlap between the first wire and the second wire connected to the two second conductive pad.