Array Substrate Signal Wiring Vertical Integration Narrow Frame
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Solution Overview
Problem
Conventional array substrates require significant space in non-display regions for peripheral wirings, such as GOA units and gate scanning circuit signal lines, which limits the design of narrow frame displays and affects the utilization efficiency of the base substrate.
Innovation Solution
The array substrate incorporates signal line wirings between a pattern layer and a base substrate within the display region, allowing signal input to signal lines without occupying additional space on the sides, using conductive materials like ITO or metal alloys to ensure efficient signal transmission without compromising display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If peripheral wirings (GOA units, gate scanning circuit signal lines) are arranged in non-display regions on both sides of the display region, then signal transmission is ensured, but the frame width increases and substrate utilization efficiency decreases
Solution Approach 1:
The patent moves the peripheral wirings from the traditional planar arrangement in non-display regions to a three-dimensional arrangement by placing them between the pattern layer and base substrate within the display region. This vertical integration allows signal transmission functionality to be achieved without increasing frame width, effectively resolving the contradiction between compact dimensions and reliable signal transmission.
2Area of stationary object
If peripheral wirings are arranged in non-display regions, then signal input is achieved, but the usable display area is reduced due to increased frame width
Solution Approach 1:
The patent merges the peripheral wiring structure with the display region by integrating signal line wirings between the pattern layer and base substrate within the display area. This consolidation eliminates the need for separate non-display regions for wiring, maximizing the usable display area while managing wiring complexity through structured integration.
Solution Approach 2:
By transitioning from a two-dimensional planar wiring layout to a three-dimensional vertical integration within the display region, the patent achieves compact wiring arrangement that does not encroach on display area, thereby increasing usable display area without excessive wiring complexity.
3Length of moving object
If signal line wirings are placed between pattern layer and base substrate, then frame width is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates signal line wirings between the pattern layer and base substrate during the manufacturing process, integrating the wiring structure into the existing layer formation steps. This preliminary integration approach minimizes additional manufacturing complexity while achieving reduced frame width, as the wirings are established alongside the standard display structure fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables narrow frame displays by eliminating the need for peripheral wiring spaces, improving substrate utilization, and reducing costs while maintaining effective signal transmission and display performance.
Implementation Method 1
signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines
Data Source
AI summary
Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines.