Array Substrate Single-Mask Patterning for Cost Reduction
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Solution Overview
Problem
The manufacturing process for array substrates in Active Matrix Liquid Crystal Displays (AMLCD) and Active-matrix organic light emitting diode (AMOLED) displays requires two metal layers to cross a gate insulation layer, necessitating complex and costly mask setups, which increases production costs and reduces efficiency.
Innovation Solution
A method where a semiconductor layer and gate insulation layer are patterned using a single mask, allowing for the simple connection of metal layers through a through hole, reducing the number of masks needed and lowering production costs while improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two different masks are used to respectively pattern the semiconductor layer and the gate insulation layer, then the manufacturing precision is improved, but the manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent combines the patterning of the gate insulation layer and semiconductor layer into a single mask step. The mask pattern includes both the gate insulation layer pattern and semiconductor layer pattern simultaneously, allowing both layers to be patterned in one exposure and development process, thereby reducing mask quantity and manufacturing cost while maintaining patterning precision
Solution Approach 2:
The single mask used in the invention serves multiple functions: it patterns both the gate insulation layer and the semiconductor layer, and also defines the through-hole alignment. This multi-functional mask design eliminates the need for separate masks for each layer, reducing overall device complexity and manufacturing cost
2Manufacturing precision
If two different masks are used to respectively pattern the semiconductor layer and the gate insulation layer, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent combines the patterning of the gate insulation layer and semiconductor layer into a single mask step. The mask pattern includes both the gate insulation layer pattern and semiconductor layer pattern simultaneously, allowing both layers to be patterned in one exposure and development process, thereby reducing mask quantity and manufacturing cost while maintaining patterning precision
Solution Approach 2:
The gate insulation layer is deposited and partially patterned before the semiconductor layer deposition. This preliminary patterning of the gate insulation layer creates a structured foundation that guides subsequent semiconductor layer formation, enabling efficient single-mask patterning while maintaining high precision
3Reliability
If two metal layers are required to cross the gate insulation layer for connection, then the electrical connectivity is improved, but the device complexity increases
Solution Approach 1:
The patent combines the patterning of the gate insulation layer and semiconductor layer into a single mask step. The mask pattern includes both the gate insulation layer pattern and semiconductor layer pattern simultaneously, allowing both layers to be patterned in one exposure and development process, thereby reducing mask quantity and manufacturing cost while maintaining patterning precision
Solution Approach 2:
The gate insulation layer serves as an intermediary that is selectively removed to form through-holes, enabling electrical connection between metal layers. This intermediary approach allows controlled electrical connectivity while maintaining the insulating function in other areas, balancing connectivity needs with device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production costs and enhances efficiency by simplifying the connection of metal layers in the array substrate, enabling cost-effective and efficient manufacturing of array substrates.
Implementation Method 1
performing a front exposing and developing to the first photoresist layer through the second mask; performing back exposing and developing to the second photoresist layer through the gate electrode and the first conductive layer
Implementation Method 2
wet etching the first photoresist layer, the semiconductor layer and the gate insulation layer after developing; wet etching the second photoresist layer and the semiconductor layer after developing
Implementation Method 3
depositing a semiconductor layer on the gate insulation layer through a physical vapor deposition (PVD) method
Data Source
AI summary
An array substrate and a manufacturing method. The method includes: patterning the first metal layer through a first mask to form a gate electrode and a first conductive layer which are disposed at an interval; patterning the semiconductor and the gate insulation layer through a second mask to form a through hole for revealing the first conductive layer; patterning the semiconductor layer through the gate electrode and the first conductive layer to form a first channel and a second channel region which are disposed at an interval; patterning the second metal layer through a third mask to form a source electrode, a drain electrode and a second conductive layer which are disposed at intervals; wherein, the second conductive layer is contacted with the first conductive layer through the through hole. Accordingly, the gate insulation and the semiconductor layer are patterned through one mask to reduce the production cost.