Array Substrate Single Patterning Process for Display Devices
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Solution Overview
Problem
Existing methods for manufacturing array substrates with oxide thin film transistors face challenges such as poor uniformity, high unit cost, and increased complexity due to multiple patterning processes, which lead to defects and reduced yield, particularly in connecting pixel and drain electrodes without via holes.
Innovation Solution
A method involving single patterning processes to form active patterns, gate electrodes, and contact structures, using transparent metal oxide conductive films, and reducing metal oxides into metal for low-resistance contacts, simplifying the formation of source, drain, and pixel electrodes directly on the contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to form active pattern, gate electrode, and contact structures separately, then each structure can be formed with precise control, but the manufacturing complexity increases and alignment accuracy decreases
Solution Approach 1:
The patent combines the formation of active pattern, gate electrode, and contact structures into a single patterning process. A photoresist pattern is formed that simultaneously defines all three structures, and a single etching process creates all required features. This merging of multiple separate patterning steps into one operation directly reduces manufacturing complexity while maintaining alignment accuracy, as all structures are defined by the same photoresist mask and processed simultaneously.
2Productivity
If pixel electrode and drain electrode are directly connected without via holes, then the number of patterning processes is reduced, but the etching solution adversely affects the active pattern
Solution Approach 1:
The patent introduces a gate insulation pattern as an intermediary protective layer between the etching solution and the active pattern. During the single patterning process, the gate insulation pattern (formed from the first insulation material film) serves as a mask that protects the active pattern from the etching solution while allowing the pixel electrode and drain electrode to be directly connected. This intermediary structure enables both manufacturing efficiency and active pattern integrity to be achieved simultaneously.
3Reliability
If polysilicon is used for thin film transistor channel formation region, then higher mobility is achieved, but uniformity deteriorates and unit cost increases
Solution Approach 1:
The patent changes the material parameter from polysilicon to oxide semiconductor material for the thin film transistor channel formation region. This material substitution maintains the desired electrical properties while improving manufacturing uniformity. The oxide semiconductor material can be deposited using sputtering or atomic layer deposition techniques that provide better film uniformity and control compared to polysilicon crystallization processes, thereby achieving both reliability and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of patterning processes, simplifies the manufacturing steps, enhances alignment accuracy, and prevents active pattern damage during etching, resulting in improved yield and reduced defects by eliminating the need for complex via holes and ensuring better electrical connections.
Implementation Method 1
reducing metal oxides into metal for low-resistance contacts
Data Source
AI summary
Embodiments of the disclosure provide an array substrate and a manufacturing method thereof, and a display device. The method includes: forming a semiconductor material film, a first insulation material film and a first conductive material film successively on a base substrate, and processing these films through a single patterning process to form an active pattern, a gate insulation pattern and a gate electrode; forming a second insulation layer and forming two contact holes in the second insulation layer and gate insulation pattern; forming a second conductive material film and forming two contact structures from portions of this layer; and forming a third conductive material film, and processing this layer through a single patterning process to form a pixel electrode, and source and drain electrodes being in direct contact with the two contact structures respectively, the pixel electrode and one contact structure being integrated into one piece.