Array Substrate Slit Design for RC Delay Reduction
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Solution Overview
Problem
As display panel sizes increase, signal line lengths and resistances also increase, leading to RC delays that degrade both display and touch performance in conventional in-cell capacitive touch screens, resulting in noise, uneven flicker, residual images, and other display errors.
Innovation Solution
The array substrate design includes common electrodes with slits and signal lines that are strategically positioned to minimize RC differences by adjusting the distance and alignment of signal lines relative to the slits, ensuring consistent capacitance and resistance products across all signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display panel size is increased, then the display area is enlarged, but the signal line length increases leading to increased RC delay and degraded display performance
Solution Approach 1:
The patent applies local quality by creating non-uniform slit configurations in different common electrodes. Specifically, common electrodes closer to the driver chip have slits with larger widths or different orientations compared to those farther away, locally adjusting the capacitance characteristics to compensate for the varying signal line lengths and RC delays across the display panel.
Solution Approach 2:
The patent changes physical parameters of the common electrodes by introducing slits with varying widths, orientations, or positions in different common electrodes. This modifies the capacitance values locally to balance the RC delay products across all signal lines, thereby maintaining consistent display performance despite the increased panel size.
2Area of stationary object
If the display panel size is increased, then the display area is enlarged, but the RC delay increases causing noise and display errors
Solution Approach 1:
The patent addresses the harmful RC delay effect by applying local quality adjustments through differentiated slit configurations. Common electrodes at different positions have slits designed with specific widths or orientations that locally modify capacitance to compensate for the varying signal line resistances, thereby reducing the overall impact of RC delay across the enlarged display panel.
Solution Approach 2:
The patent converts the harmful effect of increased capacitance (which contributes to RC delay) into a beneficial compensatory mechanism. By strategically introducing slits that increase capacitance in specific common electrodes closer to the driver chip, the design balances the RC delay products across all signal lines, transforming the potential harm into a solution that equalizes performance.
3Area of stationary object
If signal line length is increased to accommodate larger display panels, then display area is enlarged, but resistance and capacitance differences between signal lines increase
Solution Approach 1:
The patent applies local quality by designing position-dependent slit configurations in common electrodes. Signal lines of different lengths are compensated by adjusting the capacitance of adjacent common electrodes through locally varied slit parameters, thereby achieving consistent RC delay characteristics across all signal lines despite their different lengths.
Solution Approach 2:
The patent achieves equipotentiality in terms of electrical characteristics by balancing the RC delay products of all signal lines. Through careful design of slit configurations in common electrodes, the patent equalizes the effective capacitance values to compensate for resistance differences, creating a uniform electrical performance across the entire display panel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces noise and improves both touch and display performance by minimizing RC differences between signal lines, preventing recognition errors and display issues like uneven flicker and residual images.
Implementation Method 1
a first common electrode insulated from the first signal line has a first slit in a part facing to the first signal line; a second common electrode insulated from the second signal line has a second slit in a part facing to the second signal line
Data Source
AI summary
Array substrate and display panel are provided. The array substrate includes: common electrodes, first and second signal lines, wherein a common electrode insulated from the first signal line has a first slit in a part facing the first signal line, a common electrode insulated from the second signal line has a second slit in a part facing the second signal line, distance between the driver chip and a common electrode connected with the first signal line is greater than that between the driver chip and a common electrode connected with the second signal line, there are first deviation between width bisector of projection of the first signal line and width bisector of the first slit and second deviation between width bisector of projection of the second signal line and width bisector of the second slit, the first deviation is smaller than the second deviation. Display and touch performance are improved.