Array Substrate Source Gate Overlap Parasitic Capacitance
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Solution Overview
Problem
Current liquid crystal display array substrates suffer from significant parasitic capacitance between the source and gate of thin film transistors, leading to signal delay and decreased display uniformity due to overlapping areas.
Innovation Solution
The array substrate design features a thin film transistor with a source and gate connection where the orthographic projection of the source partly overlaps with the gate on the base substrate, reducing parasitic capacitance by creating non-overlapping portions, thereby minimizing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source and gate of the thin film transistor are arranged with complete overlap to improve transistor performance, then the transistor can function properly, but parasitic capacitance increases causing signal delay and cross talk
Solution Approach 1:
The source electrode is divided into multiple segments (first source electrode and second source electrode) that are positioned at different locations relative to the gate. This segmentation allows the source to maintain electrical connection while reducing the overlapping area with the gate, thereby decreasing parasitic capacitance while preserving transistor functionality.
Solution Approach 2:
The patent introduces a spatial dimension consideration by arranging the source electrodes at different positions (front and back sides of the gate line) rather than complete planar overlap. This dimensional arrangement reduces the overlapping projection area between source and gate, effectively lowering parasitic capacitance while maintaining the necessary electrical function.
2Object-generated harmful factors
If the overlapping area between source and gate is reduced to decrease parasitic capacitance, then signal delay is reduced, but the transistor performance may be compromised
Solution Approach 1:
By segmenting the source electrode into multiple parts positioned at different locations, the patent maintains sufficient overlap in critical areas for transistor function while reducing total overlapping area. This allows optimization of both transistor performance and parasitic capacitance reduction.
Solution Approach 2:
The patent applies different overlap characteristics to different segments of the source electrode. Some segments maintain overlap for proper transistor function while other segments are positioned to minimize overlap and reduce parasitic capacitance. This local differentiation optimizes both requirements simultaneously.
Data Source
AI summary
The present invention discloses an array substrate and a display device. The array substrate comprises a data line and a gate line arranged crossly, a thin film transistor being arranged in vicinity of a cross position of the data line and the gate line, the thin film transistor comprising a gate and a source, the gate being connected with the gate line, the source being connected with the data line, an orthographic projection of the source on a base substrate of the array substrate partly overlapping with an orthographic projection of the gate on the base substrate of the array substrate. The array substrate provided by the present invention can reduce the parasitic capacitance generated between the source and the gate of the thin film transistor, thereby being capable of reducing delay of the gate line signal so as to improve the display quality.