Array Substrate Source-Gate Overlap for VA Display Image Sticking
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Solution Overview
Problem
In traditional Vertical Alignment (VA) display panels, image sticking occurs due to differences in parasitic capacitance between the main and secondary regions caused by varying designs of thin film transistor (TFT) devices, leading to grayscale differences and optimal common voltage imbalances.
Innovation Solution
The design includes a first-typed active array switch in the main region and a second-typed active array switch in the secondary region, with distinct overlapping areas between the source and gate projections on the base substrate, where the first overlapping area is larger than the second, reducing the difference in gate-source parasitic capacitance and optimizing common voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If independent main region pixel electrode and independent secondary region pixel electrode are arranged alternately to realize multi-domain display, then display quality at large viewing angle is improved, but parasitic capacitance differences between main region and secondary region cause image sticking
Solution Approach 1:
The patent applies local quality by making the source electrode structures different in the main region and secondary region. Specifically, the source electrode in the main region has a different overlapping area with the gate electrode compared to the source electrode in the secondary region. This local structural differentiation compensates for the parasitic capacitance differences between regions, allowing both regions to achieve optimal common voltage and eliminate image sticking while maintaining multi-domain display quality.
2Adaptability or versatility
If different thin film transistor designs are used for main region and secondary region to charge liquid crystal capacitance, then multi-domain display is achieved, but grayscale difference occurs due to charging difference
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the source electrode in different regions. By adjusting the overlapping area between the source and gate electrodes in the main region versus the secondary region, the parasitic capacitance values are tuned to achieve uniform charging characteristics. This parameter optimization ensures that both regions reach the same common voltage level, eliminating grayscale differences while preserving multi-domain display functionality.
Data Source
AI summary
In an array substrate, a first area of overlap between projections of a first source and a first gate of an active matrix switch of a first type on a base substrate is greater than a second area of overlap between projections of a second source and a second gate of an active matrix switch a second type on the base substrate.