Array Substrate Circuit Layout for Seamless Spliced Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display technologies face challenges in achieving seamless splicing of display panels due to the presence of seams from virtual pixels, sealants, and limitations in mass transfer technology, particularly for Mini-LED and Micro-LED panels, which hinder large screen displays with uniform brightness and reduced bezel widths.
Innovation Solution
The array substrate design includes pixel groups with integrated pixel driving sub-circuits and shift register circuits arranged in a modular and centralized manner, allowing for reduced bezel widths and seamless splicing by optimizing the layout of functional sub-circuits and signal connections, including fan-out structures and side edge structures to minimize non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If pixel driving sub-circuits and shift register circuits are arranged in a modular and centralized manner, then bezel width is reduced and splicing seamlessness is improved, but device complexity increases
Solution Approach 1:
The pixel driving circuits are divided into multiple pixel driving sub-circuit groups, and the shift register circuits are segmented and arranged between different pixel groups. This segmentation allows for modular layout optimization, reducing the bezel width while maintaining manageable circuit complexity through systematic organization.
Solution Approach 2:
The patent utilizes the space between adjacent pixel groups in both row and column directions to arrange different types of circuits. By exploiting the two-dimensional layout space efficiently, the design reduces bezel width without significantly increasing circuit complexity, as circuits are placed in previously underutilized spatial regions.
2Area of stationary object
If pixel driving sub-circuit groups are disposed between adjacent rows or columns of pixels, then space utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The pixel driving circuits are segmented into sub-circuit groups that are systematically assigned to specific regions between pixel rows or columns. This segmentation creates a regular, repeating pattern that simplifies manufacturing alignment requirements compared to arbitrary circuit placements, while still achieving high space utilization.
Solution Approach 2:
Different regions of the display panel have different circuit arrangements tailored to their specific needs. Pixel driving sub-circuit groups are placed between adjacent rows or columns based on local space availability and electrical connection requirements, optimizing space utilization while maintaining feasible manufacturing precision through localized design flexibility.
3Stability of the object's composition
If shift register circuits are disposed between different pixel groups, then signal transmission uniformity is improved, but device complexity increases
Solution Approach 1:
The shift register circuits are segmented and distributed between different pixel groups rather than concentrated in one location. This segmentation creates multiple signal transmission paths that are more uniform in length and characteristics, improving signal uniformity while the systematic distribution pattern keeps the overall arrangement manageable.
Data Source
AI summary
An array substrate has a display area and includes at least one pixel group, at least one pixel circuit group and at least one shift register circuit. The at least one pixel group is disposed in the display area. Each pixel group includes a plurality of pixels arranged in an array. Each pixel circuit group is disposed between two adjacent rows of pixels or two adjacent columns of pixels in a corresponding pixel group. Each pixel circuit group includes at least one pixel driving sub-circuit group. A shift register circuit is disposed between two rows of pixels or two columns of pixels that are different from two rows of pixels or two columns of pixels between which a pixel driving sub-circuit group is disposed.


