Array Substrate Pixel Layout With Stacked Semiconductor Layers
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Solution Overview
Problem
Existing display devices with complex pixel circuits, featuring numerous transistors and capacitances, face challenges in efficiently disposing wiring due to the large number of elements and wires, which can hinder effective signal transmission and display quality.
Innovation Solution
The display device incorporates a substrate with overlapping semiconductor layers and insulating films, along with strategically layered metal and semiconductor materials, to optimize transistor and wiring configurations, reducing the number of wires needed and enhancing signal transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pixel circuit includes a large number of transistors and capacitances to achieve complex display functions, then the display functionality and versatility are improved, but the wiring complexity and device layout difficulty increase significantly
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked architecture by placing transistor layers (first and second transistor layers) at different heights above the substrate. This vertical stacking allows signal lines to connect to multiple transistor layers through vertical vias, reducing the need for complex lateral wiring while maintaining full display functionality with multiple transistors and capacitances per pixel.
Solution Approach 2:
The pixel circuit is divided into multiple discrete layers: first transistor layer, second transistor layer, and associated capacitance structures. Each layer can be independently designed and optimized, allowing complex display functions to be distributed across layers rather than concentrated in a single planar circuit, thereby reducing wiring complexity within each layer.
2Adaptability or versatility
If more wires are added to connect the large number of elements in each pixel, then the connectivity and functionality are improved, but the area occupied by each pixel increases
Solution Approach 1:
The patent utilizes vertical stacking to connect multiple transistors and capacitances within a compact footprint. By arranging transistor layers and capacitance structures in the vertical dimension rather than spreading them out laterally, the design achieves full connectivity for complex display functions while minimizing the horizontal area occupied by each pixel, thereby increasing display resolution.
Solution Approach 2:
The patent implements nested structures where capacitance electrodes are positioned between transistor layers, and signal lines pass through vertical vias that penetrate multiple layers. This nesting allows multiple functional elements to occupy overlapping spatial regions in the vertical dimension, reducing the overall pixel area while maintaining complete connectivity.
3Area of moving object
If wiring is optimized to reduce pixel area, then display resolution is improved, but signal transmission reliability and current leakage prevention become more challenging
Solution Approach 1:
The patent achieves compact pixel area through vertical stacking of transistor layers and capacitance structures. Signal transmission reliability is maintained by providing dedicated vertical via connections between layers, which offer controlled impedance paths and reduce the risk of current leakage compared to lateral wiring approaches. The insulating films between layers provide electrical isolation, preventing unwanted current paths.
Solution Approach 2:
The patent introduces insulating films as intermediary layers between conductive elements in different layers. These insulating films provide electrical isolation and prevent current leakage while allowing vertical signal transmission through controlled vias. This mediator approach enables compact wiring without compromising signal transmission reliability.
Data Source
AI summary
A display device includes a substrate, a plurality of pixels provided to the substrate, a light emitting element and a plurality of transistors provided to each of the pixels, signal lines configured to supply a signal to the pixels, a first semiconductor layer and a second semiconductor layer provided in different layers in a direction perpendicular to the substrate and overlap at least partially in planar view, first gate electrodes each of which is provided in a region overlapping a part of the first semiconductor layer, a first insulating film provided between the first gate electrodes and the first semiconductor layer, and a second insulating film provided between the first semiconductor layer and the second semiconductor layer.