Array Substrate Stacked Line Layout for Higher Pixel Aperture
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Solution Overview
Problem
Existing Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) suffer from low pixel aperture ratios due to the occupation of wiring areas by metal signal lines, leading to reduced display brightness.
Innovation Solution
The array substrate design positions the gate line on one surface and the common-electrode line on the opposite surface, with partial overlap, reducing the wiring area on the first surface and increasing the pixel-electrode layer area through the use of via holes for connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal signal lines are used to isolate various signal lines, then signal isolation is achieved, but the aperture ratio of the pixel is reduced
Solution Approach 1:
The patent moves the common-electrode line from the same plane as the gate line to an overlapping position, utilizing vertical stacking to reduce planar wiring area. This dimensional transition allows signal isolation to be maintained while minimizing the occupation of pixel area, thereby improving aperture ratio.
2Reliability
If the common-electrode line is spaced apart from the gate line, then signal isolation is maintained, but the wiring area increases
Solution Approach 1:
The patent transitions from planar separation to vertical overlapping by positioning the common-electrode line to overlap with the gate line. This dimensional change allows both signal isolation and minimal wiring area to be achieved simultaneously.
Solution Approach 2:
The patent merges the spatial occupation of the gate line and common-electrode line by positioning them to overlap, effectively combining their wiring paths in the vertical dimension while maintaining electrical isolation through the stacked structure.
3Ease of manufacture
If the gate line and common-electrode line are positioned on the same surface, then manufacturing is simplified, but the pixel aperture ratio is reduced
Solution Approach 1:
The patent resolves the contradiction by moving the common-electrode line to overlap with the gate line in the vertical dimension, maintaining manufacturing simplicity while maximizing pixel aperture ratio through reduced planar wiring occupation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases the pixel aperture ratio by approximately 10%, enhancing display brightness by optimizing the layout of signal lines.
Implementation Method 1
a first transparent conductive oxide layer is formed on the lower ITO layer
Implementation Method 2
the transparent conductive oxide layer is annealed
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
An array substrate and a method for manufacturing the same, a display panel, and a display device are provided in the disclosure. A stacked structure (200, 200') of an array substrate (100, 100') includes a contact pad (101, 101'), a common-electrode layer (20, 20'), and a gate line (121, 121'). The contact pad (101, 101') is disposed on a first surface of a base substrate (10, 10'). A common-electrode line (201, 201') of the array substrate (100, 100') is disposed on a second surface of the base substrate (10, 10'). An orthographic projection of the gate line (121, 121') on a plane where the common-electrode line (201, 201') is located at least partially overlaps with the common-electrode line (201, 201'). As such, a wiring area of the array substrate (100, 100') can be reduced, thereby increasing an aperture ratio.