Array Substrate Storage Capacitor Mask Process Reduction
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Solution Overview
Problem
The existing array substrates for liquid crystal display devices require a large number of mask processes, leading to increased manufacturing time, costs, and reduced productivity due to complex fabrication steps.
Innovation Solution
A method for manufacturing an array substrate with driver integrated circuits using a reduced number of mask processes, involving the formation of active patterns, gate electrodes, and doping ions to simplify the fabrication process, thereby reducing the complexity and time required for production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional array substrate manufacturing processes are used, then manufacturing precision and reliability are maintained, but the number of mask processes increases, leading to increased manufacturing time, costs, and reduced productivity
Solution Approach 1:
The patent combines multiple mask processes into a reduced number of mask processes by optimizing the formation of active patterns, gate electrodes, and doping ion implantation steps. This merging of processes reduces the total number of sequential operations required, directly improving productivity while maintaining manufacturing precision through careful process integration.
Solution Approach 2:
The fabrication process is segmented into distinct functional stages: active pattern formation, gate electrode formation, and doping ion implantation. Each stage is optimized independently and then integrated, allowing for streamlined processing that reduces overall complexity while maintaining the necessary manufacturing precision for each functional element.
2Loss of time
If the number of mask processes is reduced, then manufacturing time and costs decrease, but manufacturing precision may be compromised
Solution Approach 1:
The patent performs preliminary actions by pre-defining the patterns and structures required for active patterns, gate electrodes, and doping regions before final assembly. This preliminary structuring allows for fewer subsequent mask processes while maintaining precision, as the critical dimensions and alignments are established in advance through optimized process steps.
Solution Approach 2:
The patent utilizes parameter changes in the doping ion implantation process, adjusting ion types, energies, and angles to achieve precise dopant placement with fewer mask steps. By optimizing these physical parameters, the process maintains manufacturing precision while reducing the number of required mask operations and overall fabrication time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more efficient and cost-effective manufacturing process with improved productivity by reducing the number of mask processes from the traditional methods, enhancing the overall efficiency and reducing the likelihood of fabrication errors.
Implementation Method 1
forming a gate insulating layer on the substrate including the first, second and third active patterns, the extension portion and the metal pattern
Implementation Method 2
doping ions in the first, second and third active patterns
Data Source
AI summary
An array substrate for a liquid crystal display device includes a substrate including a first driving region, a second driving region, and a pixel region, the pixel region including a switching region and a storage region; a first n-type transistor in the first driving region, a second p-type transistor in the second driving region; a third transistor in the switching region, the third transistor including a gate electrode, an active layer, a source electrode, and a drain electrode; an extension portion in the storage region and extending from the active layer; a metal pattern on the extension portion; a storage line over the metal pattern; and a pixel electrode in the pixel region and contacting the third transistor, wherein the metal pattern, the storage line and the pixel electrode form first, second and third electrodes of a storage capacitor that includes a first capacitor and a second capacitor parallel to each other.