Array Substrate Storage Electrode Fabrication
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Solution Overview
Problem
The existing methods for fabricating liquid crystal display (LCD) devices with integrated driving circuits require a complex and costly multi-mask process, leading to increased processing time and defect rates due to the numerous steps involved.
Innovation Solution
A simplified method for fabricating an array substrate with an integrated driving circuit using a reduced number of mask processes, where semiconductor layers and counter electrodes are formed using a combination of polycrystalline silicon and transparent/conductive metal patterns, allowing for the integration of TFTs and storage capacitors in a more efficient manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-mask process is used to fabricate integrated driving circuits, then the integration of TFTs and storage capacitors is achieved, but the number of fabrication steps increases and production cost increases
Solution Approach 1:
The patent combines the formation of semiconductor layers and counter electrodes into a single simultaneous process step, rather than performing them separately in multiple mask steps. This merging of operations reduces the total number of fabrication steps while still achieving the desired integration of TFTs and storage capacitors in the final device structure.
Solution Approach 2:
The patent employs a universal fabrication approach where the same semiconductor layer formation process serves multiple functions: creating both the TFT active layers and the storage capacitor counter electrodes. This multi-functional process design eliminates the need for separate specialized steps, thereby reducing overall process complexity.
2Adaptability or versatility
If a multi-mask process is used to fabricate integrated driving circuits, then the integration of TFTs and storage capacitors is achieved, but processing time increases
Solution Approach 1:
The patent merges multiple sequential operations into a single simultaneous process step for forming semiconductor layers and counter electrodes. This time-saving merging eliminates the sequential waiting periods between separate mask steps, directly reducing total processing time while maintaining the integrated structure of TFTs and storage capacitors.
Solution Approach 2:
The patent performs preliminary patterning and material deposition in a unified manner before final device differentiation occurs. By establishing both TFT and storage capacitor structures in advance through a single process step, the method avoids subsequent time-consuming separate processing steps.
3Adaptability or versatility
If a multi-mask process is used to fabricate integrated driving circuits, then the integration of TFTs and storage capacitors is achieved, but the defect rate increases
Solution Approach 1:
The patent combines multiple process steps into one simultaneous operation, thereby reducing the total number of times materials are deposited, patterned, and etched. Each additional process step introduces potential failure points; by merging steps, the patent minimizes these interfaces and reduces the cumulative defect rate while still achieving proper integration.
Solution Approach 2:
The patent transforms what would normally be separate, potentially error-prone steps into a unified robust process. The simultaneous formation of multiple structures in one step creates mutual support and alignment, where the processes reinforce each other rather than complicate one another, thereby reducing defects.
Data Source
AI summary
An array substrate for a liquid crystal display (LCD) device includes a substrate including a display region and a non-display region, a driving circuit in the non-display region, at least a first thin film transistor (TFT) in the display region, a storage capacitor in the display region including a first storage electrode, a second storage electrode, and a third storage electrode, wherein the first storage electrode includes a first semiconductor layer and a counter electrode, and the third storage electrode includes a first transparent electrode pattern and a first metal pattern, a gate line and a data line crossing each other to define a pixel region in the display region, and a pixel electrode connected to the first TFT in the pixel region.