Array Substrate Support Pattern Layers for Display Stability

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Solution Overview

Problem

In liquid crystal display technology, spacers above the gate line or thin film transistor easily slide and deform, leading to non-uniform thickness of the liquid crystal cell and decreased display quality.

Innovation Solution

An array substrate design that includes a first base substrate with a gate line and data line, a thin film transistor, and support pattern layers that overlap with the gate and data lines, providing additional support to maintain uniform thickness and stability against external forces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a spacer is located above a gate line or thin film transistor, then the liquid crystal cell structure is formed, but the spacer easily slides and deforms under external force causing non-uniform thickness

Engineering Contradiction:
Improveliquid crystal cell thickness uniformityVSAvoidspacer position stability
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent introduces support pattern layers at specific locations (below the gate line and data line) to provide localized reinforcement. These support patterns are not uniformly distributed but strategically placed where spacers are positioned, creating different structural qualities in different regions of the array substrate to prevent spacer deformation while maintaining overall cell thickness uniformity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent adds a new structural dimension by introducing support pattern layers beneath the existing gate line and data line layers. This creates a multi-layer support structure where the support patterns extend in the vertical dimension, providing additional mechanical reinforcement from below to prevent spacer sliding and deformation that occurs in the planar arrangement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Stability of the object's composition

If support pattern layers are added below gate line and data line, then spacer stability is improved, but device structure becomes more complex

Engineering Contradiction:
Improvespacer position stabilityVSAvoidarray substrate structure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The support pattern layers are formed using the same materials as the existing gate line and data line (first conductive layer for gate line, second conductive layer for data line). This merging of materials and formation processes reduces device complexity by reusing existing layer structures rather than introducing entirely new materials and fabrication steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The support pattern layers serve multiple functions: they provide mechanical support to prevent spacer deformation, maintain the structural integrity of the array substrate, and are formed using the same material deposition processes as the conductive lines. This multi-functionality reduces overall device complexity by combining support and conductive functions in an integrated structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10564503B2Array substrate comprising supporting pattern layers and display device including same
Publication Date: 2020.02.18 BOE TECHNOLOGY GROUP CO LTD
  • US10564503B2 patent drawing
  • US10564503B2 patent drawing
  • US10564503B2 patent drawing

AI summary

Provided are an array substrate and a display device. The array substrate includes the array substrate. The array substrate includes at least one of a first support pattern layer and a second support pattern layer, the first support pattern layer and a gate line overlap with each other; the second support pattern layer and the data line overlap with each other, an orthogonal projection of at least one of the first support pattern layer and the second support pattern layer on the first base substrate is located outside an overlapping area of the orthogonal projections of the gate line and the data line on the first base substrate.