Array Substrate Test Lines for Display Panel Defect Detection
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Solution Overview
Problem
Current defect testing methods for display panels are inefficient and inaccurate due to the difficulty in accessing signal lines with probes, risk of signal line breakage, and inability to determine defects in both drive circuits and array substrates simultaneously.
Innovation Solution
An array substrate with integrated test lines that allow for short-circuiting and signal input/output through the test lines, enabling direct determination of defects in both drive circuits and array substrates without physically contacting the signal lines, thereby improving testing accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If probes are used to access signal lines for defect testing, then testing can be performed, but the signal lines are at risk of breakage and testing accuracy is reduced
Solution Approach 1:
The patent introduces test lines as intermediary elements that are electrically connected to signal lines through contact holes. These test lines serve as mediators between the external testing equipment and the signal lines, allowing testing to be performed without directly probing the signal lines themselves, thereby eliminating the risk of signal line breakage while maintaining testing capability
Solution Approach 2:
The patent segments the testing function by separating the test access path from the signal line path. Test lines are created as distinct conductive paths that are electrically connected to signal lines at specific points through contact holes, allowing the testing function to be separated from the signal transmission function and performed independently without affecting signal line integrity
2Reliability
If traditional probing methods are used for defect testing, then testing can be performed, but testing time is increased and efficiency is reduced
Solution Approach 1:
The patent implements preliminary action by pre-configuring test lines during the manufacturing process that extend to peripheral regions of the array substrate. These test lines are prepared in advance with proper electrical connections to signal lines through contact holes, so that when testing is needed, the test access points are already in place and readily accessible, eliminating the need for time-consuming probe positioning and access procedures
Solution Approach 2:
The test lines act as intermediary access paths that provide direct electrical connection to signal lines through contact holes. This intermediary structure enables testing equipment to access signal line electrical characteristics without physically contacting the signal lines themselves, significantly reducing testing time while maintaining comprehensive defect detection capability
3Measurement precision
If signal lines are directly probed for testing, then defects can be detected, but the complexity of the testing process increases
Solution Approach 1:
The patent segments the testing process into two independent parts: signal line operation in the display region and testing operation in the peripheral region. Test lines are confined to peripheral regions and electrically connected to signal lines through contact holes, allowing testing to be performed on test lines without interfering with signal line operation, thereby simplifying the overall testing process while maintaining detection accuracy
Solution Approach 2:
Test lines serve as intermediary elements that simplify the testing process by providing dedicated access paths to signal line electrical characteristics. Instead of directly probing signal lines which requires precise positioning and complex procedures, the test lines provide straightforward access points in peripheral regions, reducing testing process complexity while maintaining the ability to detect defects accurately
Data Source
AI summary
An array substrate, a display panel and a test method thereof and a display device. The array substrate has a display region and a peripheral region and includes a first electrode layer and a first test line. The first electrode layer includes a plurality of first signal lines arranged along a first direction, and the first signal lines extend from the peripheral region to the display region; the first test line is provided in the peripheral region, and extends along the first direction; the first test line is overlapped with and insulated from the first signal lines.