Array Substrate Test Pad Layout for Narrow Border Display Panels
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Solution Overview
Problem
The existing visual testing (VT) circuit in display panels is complex, occupies significant space, and restricts the manufacturing of narrow lower non-display borders, leading to insufficient charging capacity and increased risk of Electro-Static Discharge (ESD) shocks during the manufacturing process.
Innovation Solution
The redesign of the array substrate eliminates the need for the VT circuit by using first and second pads with test parts in peripheral areas to transmit test signals directly to display signal lines, reducing power consumption and space occupancy, while improving driving capacity and eliminating ESD risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a VT circuit is used for visual testing, then testing functionality is achieved, but the lower non-display border width increases
Solution Approach 1:
The patent extracts the testing functionality from the traditional VT circuit and integrates it directly into the data signal lines. The test parts are formed in the same pixel electrodes as the display parts, eliminating the need for separate VT circuit components and reducing the lower non-display border width while maintaining visual testing capability.
Solution Approach 2:
The patent merges the testing function with the data signal lines by forming test parts and display parts in the same pixel electrodes. The data signal lines serve dual purposes: driving display pixels and conducting visual testing signals, thereby combining multiple functions into a single structure and reducing space requirements.
2Reliability
If a VT circuit is used for visual testing, then testing functionality is achieved, but power consumption increases
Solution Approach 1:
The patent merges the testing function with the data signal lines, allowing the same signal lines to be used for both display driving and visual testing. This eliminates the need for separate power supply circuits for VT components, thereby reducing overall power consumption while maintaining testing functionality.
3Reliability
If a VT circuit is used for visual testing, then testing functionality is achieved, but ESD shocks and damages occur
Solution Approach 1:
The patent extracts the testing functionality from the VT circuit and integrates it into the data signal lines and pixel electrodes. By eliminating separate VT circuit components that are vulnerable to ESD, the design reduces ESD shocks and damages while maintaining visual testing capability through the existing robust data signal infrastructure.
4Area of stationary object
If components in the VT circuit are made in small sizes, then space is saved, but VT charging capacity becomes insufficient
Solution Approach 1:
The patent merges the testing function with the data signal lines, which already have sufficient width and charging capacity for driving display pixels. By using the existing data signal lines for visual testing instead of creating separate narrow VT signal lines, the design maintains adequate charging capacity while saving space.
Data Source
AI summary
An array substrate, and a display panel and a test method therefor are provided. The array substrate includes a plurality of display signal lines disposed in a display area, and a plurality of first pads and a plurality of second pads disposed in a peripheral area around the display area and electrically connected to the respective plurality of display signal lines. A first test area and a second test area are disposed in a first direction on two sides of a primary area respectively. The first pad includes a first primary part and the second pad includes a second primary part. The first primary parts and the second primary parts are disposed in the primary area and are disposed alternately in a second direction.