Array Substrate Test Pixel Opening for TFT Accuracy
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Solution Overview
Problem
The existing array substrate in ADS mode lacks an accurate method to test the performance of thin film transistors in the display region due to structural differences between the edge and display regions, leading to unreliable test results.
Innovation Solution
Incorporating test pixel units with openings in the insulating layer above the pixel electrode, separated from the common electrode, allowing direct contact and signal transmission for testing, and optionally using a conductive pin contacting structure connected through these openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test thin film transistors are provided in the edge region, then thin film transistor testing becomes possible, but the test results cannot accurately reflect the performance of thin film transistors in the display region due to different process environments
Solution Approach 1:
The array substrate is divided into display region and edge region, with test pixel units specifically located in the edge region. This segmentation allows dedicated testing functionality while maintaining the integrity of the display region.
Solution Approach 2:
Test pixel units are created as copies of normal pixel units, containing identical thin film transistors manufactured in the same process. These test pixel units replicate the structure and manufacturing conditions of display region pixels, ensuring test results accurately reflect display region performance.
2Reliability
If the insulating layer is made complete above the pixel electrode, then the pixel electrode is protected, but the test pin cannot contact the pixel electrode for testing
Solution Approach 1:
An opening is created in the insulating layer above the pixel electrode in test pixel units, extracting the protective function locally to enable test pin contact. This allows testing while maintaining protection in other areas where the insulating layer remains complete.
Solution Approach 2:
The opening in the insulating layer serves as an intermediary pathway, allowing the test pin to contact the pixel electrode through the insulating layer without compromising the overall protective function of the insulating layer structure.
3Stability of the object's composition
If the common electrode is provided continuously above the insulating layer, then the electrode structure is complete, but it interferes with the test pin contact to the pixel electrode
Solution Approach 1:
The common electrode is removed or creates an opening in the region above the pixel electrode in test pixel units, extracting the continuous electrode structure locally to allow test pin access while maintaining the electrode's functional completeness in display regions.
Solution Approach 2:
The common electrode structure is made different in test pixel units versus normal pixel units. In test pixel units, the common electrode is configured to allow pin contact, while in normal pixel units it maintains continuous coverage for proper display function.
Data Source
AI summary
The invention discloses an array substrate, a display panel and a display device, and belongs to the field of array substrate test technology, which can solve the problem that the performance of the thin film transistor at the display region of the array substrate in an ADS mode cannot be accurately tested. The array substrate in the invention comprises a plurality of pixel units, each of which comprises a pixel electrode, an insulating layer above the pixel electrode, and a common electrode above the insulating layer, wherein at least one of the pixel units is a test pixel unit, wherein an opening is provided in the insulating layer of the test pixel unit to be above the pixel electrode and separated from the common electrode. The display panel and the display device in the invention comprise the above array substrate.