Array Substrate Test Switch Circuit Narrowing Display Borders
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Solution Overview
Problem
Existing display devices have wider borders, which limits their aesthetic appeal and functionality in consumer electronics.
Innovation Solution
The design of an array substrate with a test switch circuit that connects or disconnects data signal lines and test pad groups, allowing for testing while reducing the size of the lower border by positioning the test pad group in the chip bonding region and the test switch circuit away from it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the test pad group is positioned in the chip bonding region and the test switch circuit is positioned away from the chip bonding region, then the lower border size is reduced achieving narrow borders, but the device complexity increases due to the need for additional test switch circuit and positioning arrangements
Solution Approach 1:
The patent divides the peripheral region into distinct functional zones: the chip bonding region for chip attachment and the test switch circuit region for testing functionality. This spatial segmentation allows the test pad group to be positioned in the chip bonding region while the test switch circuit is positioned separately, enabling narrow border design without compromising testing capability.
Solution Approach 2:
The test switch circuit acts as an intermediary component that connects the test pad group (positioned in the chip bonding region) to the data signal line. This intermediary allows the test pad group to be relocated to the chip bonding region for border reduction while maintaining electrical connectivity through the test switch circuit positioned in the peripheral region.
2Length of stationary object
If the test pad group is positioned in the chip bonding region, then the lower border is narrowed, but the ease of manufacture decreases due to tighter spatial constraints and more complex routing
Solution Approach 1:
The patent utilizes the vertical dimension (different layers of the substrate) to route test traces and position components. By employing multi-layer routing, the test switch circuit can be positioned in the peripheral region while connecting to the test pad group in the chip bonding region, accommodating tight spatial constraints without compromising manufacturability.
Solution Approach 2:
The test switch circuit provides dynamic connectivity by being configurable to connect or disconnect the data signal line from the test pad group. This dynamic switching capability allows flexible routing arrangements that can be optimized for both narrow border design and manufacturing ease, as the connections can be adjusted during testing without permanent structural modifications.
Data Source
AI summary
The present disclosure provides a display device and an array substrate. The array substrate includes: a substrate, and a pixel circuit, a data signal line, a test pad group, and a test switch circuit that are provided on a side of the substrate, where the data signal line is electrically connected to the pixel circuit, the test pad group is in the chip bonding region, the test switch circuit is in the peripheral region and at a side of the pixel region away from the chip bonding region, and the test switch circuit is configured to connect or disconnect the data signal line and the test pad group.