Array Substrate Testing Structure for Narrow Frame Design
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Solution Overview
Problem
Existing array substrates for touch panels face challenges in testing for short or broken circuits due to the large size of testing signal terminals, which occupy excessive space and hinder the design of narrow frames in electronic devices.
Innovation Solution
The array substrate design includes receiving test signal pins and bonding pins of similar size, arranged in a row on the non-display region, with a position strip and fixing element to facilitate compact positioning and testing, allowing for efficient signal transmission and reducing the width of the non-display region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If testing signal terminals are made large for probe positioning convenience, then ease of operation is improved, but the area occupied increases and narrow frame design becomes difficult
Solution Approach 1:
The patent merges the testing signal terminals with the bonding pins, making them integrated components rather than separate structures. This allows the testing function to be performed using the existing bonding pin structure, eliminating the need for separate large testing terminals and thus reducing the occupied area while maintaining operational functionality.
Solution Approach 2:
The bonding pins are designed to serve dual purposes: both for bonding connections and for receiving testing signals. This multi-functionality eliminates the need for dedicated testing terminals, thereby reducing the overall area occupied in the non-display region while maintaining both bonding and testing capabilities.
2Reliability
If multiple testing terminals are arranged to accommodate all test signals, then completeness of testing is improved, but the width of non-display region increases
Solution Approach 1:
The patent transitions from arranging testing terminals in a horizontal layout (consuming width) to a vertical arrangement along the bonding pin structure. By utilizing the vertical dimension for signal reception and processing, the design accommodates multiple test signals without increasing the horizontal width of the non-display region, thus maintaining compactness while ensuring complete testing coverage.
Data Source
AI summary
An array substrate and an array substrate testing structure are provided. The array substrate includes a display region and a non-display region, a plurality of receiving test signal pins, a plurality of bonding pins and a plurality of transmission lines are positioned on the non-display region, the receiving test signal pins and the transmission lines are arranged in row. This invention decreases width of non-display region of electrical device such that easily to design the narrow frame.