Array Substrate Motherboard Testing Pad Design
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Solution Overview
Problem
The electro-static discharge phenomenon at the contacting via holes of bridge circuits in TFT-LCD testing can lead to breakdown of gate lines, resulting in abnormal lighting issues during testing of liquid crystal cells.
Innovation Solution
The array substrate motherboard is designed with gate line and data line testing leads and pads made of the same material, in the same layer, allowing direct connection without via holes, and includes dummy and common testing pads, along with an insulating layer between data line testing leads and driving leads, to mitigate electro-static discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bridge circuits are used to connect gate lines and testing lines, then testing functionality is achieved, but electro-static discharge occurs at via holes causing gate line breakdown
Solution Approach 1:
The patent removes the bridge circuit structure and via holes from the testing path. Instead of routing testing signals through bridge circuits that require via holes, the invention creates direct testing leads from testing pads to gate lines, eliminating the problematic intermediate connection points where electro-static discharge occurs.
Solution Approach 2:
The patent introduces testing leads as intermediary elements that provide a direct conductive path between testing pads and gate lines. These testing leads serve as dedicated intermediaries that bypass the bridge circuit structure, allowing testing signals to reach gate lines without passing through vulnerable via holes.
2Reliability
If via holes are used in bridge circuits for connection, then circuit connectivity is achieved, but electro-static discharge damages occur
Solution Approach 1:
The patent extracts and eliminates via holes from the testing signal path. By designing testing leads that connect directly to gate lines without requiring via holes, the invention removes the vulnerable connection points that generate electro-static discharge damage while maintaining testing connectivity.
3Reliability
If testing leads are made larger in width than testing pads, then contacting area is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary action by designing testing pads with larger widths than the testing leads that connect to them. This preliminary design choice ensures that when testing leads are positioned on the larger pads, alignment tolerances are more forgiving, and contacting effectiveness is improved without requiring extremely high manufacturing precision.
Data Source
AI summary
An array substrate motherboard includes a substrate including a plurality of gate lines, a plurality of gate line driving leads, a plurality of data lines, and a plurality of data line driving leads; a plurality of gate line testing leads; a plurality of data line testing leads and a plurality of data line driving leads; a plurality of gate line testing pads; a plurality of data line testing pads; and an insulating layer arranged between the data line testing leads and the data line driving leads in the trimming region. A respective one of the plurality of data line testing pads is connected with a respective one of the plurality of data line testing leads. A respective one of the plurality of data line driving leads is connected with one of the plurality of data line testing leads that penetrate through the insulating layer.