Array Substrate Three-Mask Manufacturing Method
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Solution Overview
Problem
The existing manufacturing processes for array substrates in TFT-LCDs are complex, costly, and have low yield due to the numerous steps involved in photomask technologies, such as 5 mask or 4 mask technologies, which lead to high production costs and inefficiencies.
Innovation Solution
A simplified manufacturing method for array substrates using only three mask manufacturing processes, where a first mask forms scan lines and TFT gates, a second mask forms data lines and electrodes, and a third mask forms a doped active layer and transparent conducting layers, reducing the number of steps and materials needed while ensuring reliable electrical connections and a symmetrical TFT structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If 5 mask or 4 mask technology is used to manufacture array substrate, then the manufacturing precision and reliability are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple mask processes into a single mask by integrating the pixel electrode pattern, transparent conducting layer pattern, and doped active layer pattern into one unified mask structure. This merging of multiple patterning steps into one process reduces device complexity while maintaining the required manufacturing precision through the integrated design of the mask itself
Solution Approach 2:
The single mask used in the patent serves multiple functions simultaneously: it defines the pixel electrode pattern, the transparent conducting layer pattern, and the doped active layer pattern. This multi-functional mask eliminates the need for separate masks for each layer, reducing the number of processes while achieving the same patterning precision that would otherwise require multiple specialized masks
2Manufacturing precision
If multiple mask manufacturing processes are used, then the manufacturing precision is improved, but the productivity decreases and manufacturing time increases
Solution Approach 1:
The patent merges multiple sequential mask-based patterning processes into a single parallel process by using one mask to simultaneously define multiple patterns (pixel electrode, transparent conducting layer, doped active layer) in different layers. This eliminates the sequential nature of multiple mask processes, thereby increasing substrate manufacturing throughput while preserving patterning precision
Solution Approach 2:
The patent enables continuous manufacturing by eliminating the interruptions and intermediate steps associated with multiple mask processes. The single mask process allows for uninterrupted deposition and patterning operations, maintaining continuous production flow and maximizing substrate manufacturing throughput without sacrificing the precision required for electrode and active layer formation
3Manufacturing precision
If multiple mask manufacturing processes are used, then the manufacturing precision is improved, but the loss of time and manufacturing cost increase
Solution Approach 1:
The patent combines multiple time-consuming mask processes into a single mask operation that simultaneously patterns multiple layers and structures. This merging eliminates the cumulative time loss from sequential processing steps while maintaining the precision required for TFT gate, source/drain electrodes, and active layer formation through the integrated mask design
Solution Approach 2:
The patent performs preliminary pattern design and mask fabrication in advance, creating a single comprehensive mask that contains all necessary pattern information for multiple layers. This preliminary action eliminates the need for repeated mask fabrication and alignment processes, reducing total manufacturing cycle time while ensuring consistent precision across all TFT structures
4Reliability
If 5 mask or 4 mask technology is used, then the reliability of electrical connections is improved, but the ease of manufacture decreases
Solution Approach 1:
The patent merges the patterning of electrically connected structures (pixel electrode, transparent conducting layer, doped active layer) into a single mask process, simplifying the manufacturing procedure while maintaining reliable electrical connections through the integrated design that ensures proper alignment and connectivity of all conductive elements
Solution Approach 2:
The patent uses the single integrated mask as an intermediary tool that simultaneously defines patterns for multiple electrically connected layers. This intermediary approach simplifies manufacturing by eliminating the need for multiple separate masking operations while ensuring that the electrical connections between pixels, conductors, and active regions are reliably established through the unified patterning process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and cost, enhances yield, and simplifies the process by eliminating unnecessary steps, resulting in a more efficient and cost-effective production of array substrates for liquid crystal display devices.
Implementation Method 1
A photoresistor formed in the second mask manufacturing process is incinerated to expose the n+a-Si film on both ends of the conducting channel
Implementation Method 2
an a-Si film is paved on the surface of the array substrate, and the formed a-Si film and the n+a-Si film on both ends of the conducting channel are reliably and electrically connected
Data Source
AI summary
A manufacturing method of the array substrate includes the steps: A. A first mask manufacturing process is adopted to from scan lines and thin film transistor (TFT) gates on a surface of a substrate. B. A second mask manufacturing process is adopted to form scan lines and data lines of the array substrate, a source electrode and a drain electrode of TFT and a conducting channel positioned between the source electrode and the drain electrode. C. A photoresistor formed in the second mask manufacturing process is incinerated, and then, an a-Si film is paved on the surface of the array substrate. D. The photoresistor is stripped to form an undoped active layer. E. A third mask manufacturing process is adopted to form a transparent conducting layer on the surface of the drain electrode of the TFT. Only three mask manufacturing process in the present disclosure are needed to manufacture the entire array substrate.