Array Substrate Through Hole Etching Control
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Solution Overview
Problem
The existing manufacturing processes for TFT-LCD array substrates face issues with poor connections between upper and lower layers due to over-etching of the passivation layer through holes, leading to potential circuit breaks and reduced contact areas.
Innovation Solution
The proposed solution involves forming a base substrate with a thin-film transistor, a first conductive layer, and a passivation layer, where a through hole in the passivation layer ensures that its projection falls within the projections of both the first and second conductive layers, preventing complete etching and maintaining electrical connections, and includes an annealing treatment for the conductive layers to enhance stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the passivation layer through hole is etched deeply to ensure connection, then the connection reliability is improved, but the risk of over-etching increases causing circuit breaks
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the passivation layer and the conductive layers. This buffer layer acts as a protective mediator that prevents the etching process from penetrating too deeply and damaging the conductive layers, thus resolving the contradiction between achieving deep connection and avoiding over-etching damage.
Solution Approach 2:
The buffer layer is designed with specific material properties and thickness beforehand to cushion the etching process. By pre-positioning this protective layer, the patent ensures that even if etching parameters vary, the conductive layers are protected from damage, thus preventing over-etching harm while maintaining connection reliability.
2Productivity
If the manufacturing process is simplified to reduce costs, then the productivity is improved, but the manufacturing precision may deteriorate
Solution Approach 1:
The patent changes the material parameters of the buffer layer (using materials with different etching rates than the passivation layer) to create a self-limiting etching process. This parameter change allows the etching to stop automatically at the buffer layer, improving precision without requiring complex process control, thus maintaining productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively avoids the risks of over-etching and ensures reliable connections between layers, preventing circuit breaks and maintaining structural integrity, thus improving the manufacturing process and reducing costs by optimizing the use of masks.
Implementation Method 1
the conductive layer is a conductive layer subjected to annealing treatment
Data Source
AI summary
An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a thin-film transistor and a first conductive layer formed on the base substrate; and a passivation layer formed on the TFT and the first conductive layer. The TFT includes a source electrode and a drain electrode; the first conductive layer is arranged in the same layer with the source electrode and the drain electrode; a second conductive layer is disposed on a side of the first conductive layer opposite to the passivation layer; the passivation layer is provided with a through hole penetrating therethrough; and an orthographic projection of the through hole on the base substrate falls within an orthographic projection of the first conductive layer on the base substrate and falls within an orthographic projection of the second conductive layer on the base substrate.