Array Substrate Touch Electrode Hollowing for Capacitance Reduction
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Solution Overview
Problem
In capacitive touch screen panels, the overlap between touch electrodes and gate lines leads to increased coupling capacitance, affecting touch accuracy and display quality due to insufficient pixel charging rate and light interference.
Innovation Solution
The array substrate design includes touch electrodes with hollowed-out areas at positions of gate lines, reducing overlap and coupling capacitance, and incorporates a self-capacitance and mutual capacitance integrated technology with a wavy data line structure to enhance touch accuracy and display effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If touch electrodes overlap with gate lines to simplify structure, then device complexity is reduced, but coupling capacitance increases affecting touch accuracy
Solution Approach 1:
The patent extracts the problematic overlapping region by creating hollowed-out areas in the touch electrodes where they would otherwise overlap with gate lines. This removes the source of coupling capacitance while maintaining the overall simplified structure, directly resolving the contradiction between structural simplicity and touch accuracy.
Solution Approach 2:
The patent applies local quality by making the touch electrode non-uniform - solid in most areas for structural integrity and conductivity, but hollowed-out specifically at regions where gate lines pass through. This localized modification reduces coupling capacitance only where necessary without compromising the overall electrode function.
2Area of moving object
If touch electrode area is increased to improve touch sensitivity, then touch sensitivity is improved, but coupling capacitance with gate lines increases
Solution Approach 1:
The patent extracts the harmful overlapping portions from the touch electrode area. By creating hollowed-out regions at gate line intersections, the effective area contributing to coupling capacitance is reduced while the overall electrode dimensions and sensitivity can be maintained or optimized.
Solution Approach 2:
The patent applies local quality by differentiating the touch electrode structure - full coverage areas provide sensitivity while hollowed-out areas at gate line intersections eliminate coupling capacitance. This allows the electrode to have large overall area for sensitivity without proportionally increasing harmful overlap.
3Ease of manufacture
If data lines are arranged in straight lines to simplify manufacturing, then ease of manufacture is improved, but light interference and display quality deteriorate
Solution Approach 1:
The patent applies curvature by designing data lines as wavy structures rather than straight lines. This curved configuration reduces regular light interference patterns and moire effects while remaining compatible with standard manufacturing processes, resolving the contradiction between manufacturing simplicity and display quality.
4Speed
If pixel charging rate is increased to improve display refresh rate, then display refresh rate is improved, but power consumption increases
Solution Approach 1:
The patent converts the harmful coupling capacitance between touch electrodes and gate lines into a benefit by reducing it. Lower coupling capacitance decreases the charge required to charge pixel electrodes during display refresh, thereby improving pixel charging rate while reducing power consumption - achieving both goals simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption, improves touch accuracy, and increases pixel charging rate while minimizing light interference, resulting in enhanced display quality and support for multi-touch functions.
Implementation Method 1
the overlap between touch electrodes and gate lines leads to increased coupling capacitance
Data Source
AI summary
The present disclosure provides an array substrate and a display device. The array substrate includes: a base substrate; a plurality of gate lines on the base substrate; and a touch electrode layer located on a side, away from the base substrate, of a layer where the gate lines are located. The touch electrode layer includes a plurality of touch electrodes, and the touch electrodes are provided with first hollowed-out areas at the positions of at least part of the gate lines.