Array Substrate Peripheral Wiring via Transfer Structures
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Solution Overview
Problem
The periphery of the display area in TFT-LCDs is prone to rubbing alignment shadows and uneven liquid crystal diffusion due to the peripheral wiring area, leading to abnormal display conditions such as peripheral dark state light leakage or bright state dark areas, and reducing the yield of display products.
Innovation Solution
An array substrate is designed with a display area and a peripheral wiring area, where the thin film transistor and common electrode are formed on a base substrate, and the peripheral wiring area includes a first lead, gate signal line, and common signal line. The first transfer structure, comprising via holes and a transfer portion, is used to connect the gate signal line and first lead, while the second transfer structure connects the common signal line and second lead, both structures being located away from the display area to minimize interference with liquid crystal orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the peripheral wiring area is present in conventional TFT-LCD, then the display area can be formed with necessary electrical connections, but the periphery of the display area is prone to rubbing alignment shadows and uneven liquid crystal diffusion
Solution Approach 1:
The patent extracts and removes the peripheral wiring area from the conventional display structure. By eliminating the peripheral wiring area that causes rubbing alignment shadows and uneven liquid crystal diffusion, the invention achieves better display quality at the periphery without the harmful effects of traditional wiring configurations.
Solution Approach 2:
The patent transitions from a planar wiring arrangement to a three-dimensional structure by stacking the wiring area beneath the display area. This dimensional change allows electrical connections to be maintained while removing the peripheral wiring from the surface where it causes alignment shadows and liquid crystal diffusion issues.
2Reliability
If the peripheral wiring area is present in conventional TFT-LCD, then electrical connections can be established, but abnormal display conditions such as peripheral dark state light leakage or bright state dark areas occur
Solution Approach 1:
The patent extracts the harmful peripheral wiring area that generates light leakage and dark area defects. By removing this problematic structure while maintaining necessary electrical connections through alternative routing, the invention eliminates the source of peripheral display abnormalities.
Solution Approach 2:
The patent introduces a buffer layer as an intermediary structure between the wiring area and the liquid crystal layer. This buffer layer mediates the interaction, allowing electrical connections to function while preventing the wiring area from directly causing light leakage and dark area defects in the display.
3Productivity
If the peripheral wiring area is present in conventional TFT-LCD, then the display can function, but the yield of display products is reduced
Solution Approach 1:
The patent removes the peripheral wiring area that causes display defects and reduces product yield. By eliminating the source of rubbing alignment shadows, uneven liquid crystal diffusion, and peripheral display abnormalities, the invention increases the proportion of defect-free displays and improves overall manufacturing yield.
Data Source
AI summary
The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display apparatus. The array substrate has a display area and a peripheral wiring area provided at at least one side of the display area. The display area includes a thin film transistor and a common electrode formed on the base substrate; the peripheral wiring area includes a first lead, a gate signal line and a common signal line formed on the base substrate; the first lead and the gate electrode of the thin film transistor are arranged in an identical layer and are electrically connected; the gate signal line is located on a side of the first lead away from the base substrate, and is electrically connected to the first lead through a first transition structure.