Array Substrate Frame Width Reduction via Transistor Segmentation
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Solution Overview
Problem
Current liquid crystal display technologies face challenges in achieving a narrow frame design due to the integration process of the gate driver on the array substrate, which complicates the wiring layout and affects the frame width.
Innovation Solution
The array substrate design includes a base substrate with a display area and a frame area, where shift registers with transistors are arranged such that the first transistor of each stage is located in the display area, connected to both the current and next gate line, and signal lines are distributed between the display and frame areas, allowing for a reduced frame width without complicating the wiring layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the gate driver is integrated on the array substrate through GOA process, then the frame width is reduced and productivity is improved, but the wiring layout becomes complicated
Solution Approach 1:
The invention divides the transistors in each shift register stage into two groups: first transistors located in the display area and second transistors located in the frame area. This segmentation allows different parts of the circuit to be positioned in different regions, simplifying the wiring layout while maintaining the integrated gate driver structure.
Solution Approach 2:
The invention applies local quality by placing specific transistors (first transistors) in the display area and others (second transistors) in the frame area based on their functional requirements. This localized positioning optimizes the wiring complexity in each region separately, reducing overall layout complexity while achieving narrow frame design.
2Device complexity
If all transistors are located in the frame area, then the wiring layout is simplified, but the frame width increases
Solution Approach 1:
The invention utilizes both the display area and frame area dimensions to distribute transistors. By placing first transistors in the display area and second transistors in the frame area, the solution effectively uses spatial distribution across different regions to reduce frame width while managing wiring complexity through strategic positioning.
3Area of moving object
If signal lines are all located in the frame area, then the display area is preserved, but the frame width increases
Solution Approach 1:
The invention segments signal lines into two categories: first signal lines connected to first transistors are located in the display area, while second signal lines connected to second transistors are located in the frame area. This segmentation allows signal routing to be distributed across both regions, preserving display area while reducing the required frame width.
Data Source
AI summary
An array substrate and a display panel are disclosed. The array substrate comprises shift registers corresponding to respective gate lines. The transistor in each stage of shift register connected with a corresponding stage of gate line and a next stage of gate line is a first transistor. The signal line connected with the first transistor in a plurality of signal lines connected with the shift register is a first signal line. The first transistor and the signal line connected with the first transistor are arranged in the display area, which can reduce the width of the frame area without completing the wiring layout design of the array substrate.