Array Substrate with Reduced Transistor Count for High Light Transmittance

The patent applies local quality by differentiating the pixel driving circuit configurations between first and second display regions. The first region uses a reduced transistor count (e.g., 2T1C configuration) optimized for high light transmittance applications like camera integration, while the second region uses a full transistor count (e.g., 4T1C or more) for standard display performance. This localized optimization allows each region to have tailored electrical characteristics matching its functional requirements.

The patent segments the display region into multiple areas with different pixel driving circuit designs. By dividing the display panel into first and second regions with distinct transistor configurations, the system can simultaneously achieve high light transmittance in the camera region and full functionality in standard display regions, resolving the contradiction between these competing requirements.

The patent utilizes multi-layer signal line architecture where signal lines are distributed across different conductive layers. This vertical dimensionality allows signal lines to overlap in the planar view without physically blocking each other, maintaining light transmittance while providing multiple functions. The stacked layer structure enables high functionality without increasing the footprint or blocking light paths.

The patent merges multiple signal line functions into shared pathways where possible. By having signal lines from different layers serve multiple pixel regions simultaneously, the design reduces the total number of discrete signal lines needed, thereby minimizing non-transparent components while maintaining versatility.