Array Substrate Mask Reduction via Transparent Gate Electrode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional bottom-gate LTPS TFT-LCD manufacturing processes require numerous masks, increasing complexity and cost, and result in non-uniform brightness due to thick organic layers, leading to a low yield rate.
Innovation Solution
A simplified manufacturing method for array substrates that reduces the number of masks needed by forming electrodes and semiconductor layers in a sequence, using a transparent conductive film between the gate and substrate, and forming through holes to expose semiconductor areas, thereby reducing the thickness of insulation layers and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bottom-gate LTPS manufacturing process is used, then the display function is achieved, but the number of masks increases to nine or more, increasing manufacturing complexity and cost
Solution Approach 1:
The patent merges the formation of the first electrode and gate electrode into a single manufacturing step by depositing them as a combined layer structure. The first electrode layer and gate electrode layer are formed simultaneously, and patterned together using a single mask, reducing the total mask count from nine to six while maintaining the bottom-gate LTPS TFT functionality
Solution Approach 2:
The first electrode layer serves multiple functions: it acts as both the first electrode (for storage capacitor) and as part of the gate electrode structure. This multi-functional design allows a single deposited layer to fulfill multiple electrical roles, reducing the number of separate electrode formation steps and masks required
2Reliability
If thick organic layer is used for isolating metallic electrode and transparent electrode, then the parasitic capacitance is decreased, but the manufacturing process becomes critical and display brightness uniformity deteriorates
Solution Approach 1:
The patent extracts and eliminates the thick organic layer from the structure by directly forming the first electrode on the substrate without requiring thick organic insulation. The storage capacitor is formed using the first electrode, second electrode, and dielectric layer, removing the need for thick organic layers that caused brightness uniformity issues while still achieving adequate isolation and capacitance reduction
3Reliability
If thick organic layer is used for electrode isolation, then parasitic capacitance is reduced, but the yield rate decreases due to non-uniform brightness
Solution Approach 1:
The patent removes the problematic thick organic layer from the manufacturing process by adopting a direct electrode formation approach on the substrate. The storage capacitor structure uses the first electrode, second electrode, and dielectric layer without requiring thick organic insulation, thereby eliminating the source of non-uniform brightness and improving yield rate while maintaining adequate parasitic capacitance reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and improves display brightness uniformity by minimizing the number of masks required from nine to six, enhancing yield rates and reducing manufacturing complexity.
Implementation Method 1
a transparent conductive film is provided between the gate electrode and the substrate
Implementation Method 2
excimer laser is adopted as a heat source. After passing through a projection system, laser may generate laser beams with uniform energy for projecting on the a-Si glass substrate. After absorbing the energy from the excimer laser, the a-Si glass substrate transforms into the poly-silicon
Implementation Method 3
the a-Si glass substrate transforms into the poly-silicon. The temperature of the overall process is under 600° C.
Data Source
AI summary
A manufacturing method of array substrates, an array substrate, and a display panel are disclosed. The manufacturing method of the array substrate includes: forming a first electrode and a gate electrode on a substrate in sequence; forming an insulation layer, a semiconductor layer and a dielectric layer on the substrates in sequence and forming a first through hole, a second through hole and a third through hole; forming a source electrode, a drain electrode, a second electrode and a third electrode on the dielectric layer, wherein the source electrode and the drain electrode connect to the semiconductor layer respectively, the second electrode connects to the first electrode and the third electrode connects with the drain electrode. In this way, the number of the masks needed during the manufacturing process is decreased. In addition, the manufacturing process is simplified and the cost is reduced.