Array Substrate Trenches for LCD Signal Delay Reduction
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Solution Overview
Problem
As LCDs increase in size, the longer gate and data lines lead to increased signal resistance, causing signal delay, deformation, and operation defects, which are exacerbated by attempts to increase thickness or width, resulting in reduced aperture ratio, insulation degradation, and potential short-circuits.
Innovation Solution
The array substrate features trenches of specific depth and width filled with metal materials through electroless plating, allowing for thicker gate and data lines without step protrusions, maintaining a flat surface and reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness or width of gate and data lines is increased to reduce signal resistance, then signal delay is reduced, but aperture ratio is reduced and step portions are created causing insulation degradation
Solution Approach 1:
The patent transitions from increasing line width (2D plane) to increasing line thickness (3D depth) by forming gate and data lines within trenches of specific depth. This dimensional change allows thicker lines that reduce resistance without occupying additional planar space, thereby maintaining aperture ratio while improving signal transmission quality.
2Reliability
If the thickness of gate and data lines is increased to reduce signal resistance, then signal delay is reduced, but step portions are created causing insulation degradation and potential short-circuits
Solution Approach 1:
The gate and data lines are nested within trenches formed in the substrate, with the trench depth controlling the line thickness. This nesting approach allows thick conductive lines to be embedded without creating protruding step portions on the surface, eliminating the insulation degradation and short-circuit risks associated with traditional thick lines.
3Reliability
If the width of gate and data lines is increased to reduce signal resistance, then signal delay is reduced, but aperture ratio is reduced
Solution Approach 1:
Instead of increasing line width in the planar dimension to reduce resistance, the patent increases line thickness in the vertical dimension by forming lines within trenches. This allows the conductive cross-section to increase for better signal transmission while maintaining the same planar footprint, thereby preserving aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables thicker signal lines without increasing step portions, reducing signal delay and defects, while maintaining insulation integrity and preventing short-circuits, thus enhancing display quality and reducing production costs.
Implementation Method 1
filled with metal materials through electroless plating
Data Source
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AI summary
An array substrate includes: a trench having a depth from a surface of a substrate; a gate line, a gate electrode and a data pattern filling the respective trenches, wherein the data pattern is between the adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose both ends of the data pattern, respectively; a data connection portion on the gate insulating layer and contacting the adjacent data patterns through the contact holes; a source electrode extending from the data connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole.