Array Substrate Two-Mask Etching Process

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Solution Overview

Problem

Conventional vertical alignment (VA) display manufacturing processes require at least four steps, increasing manufacturing costs due to complexity and inefficiency, which hinders cost-effective mass production.

Innovation Solution

A method for manufacturing an array substrate using only two masks to form a first metal layer with a gate, a gate insulation layer, and a second metal layer with a source, drain, and pixel electrode, enhancing efficiency and reducing costs by simplifying the process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional VA manufacturing process is used with at least four processes (M1, active layer, M2, PV, pixel electrode), then the display quality is maintained, but the manufacturing cost increases and manufacturing efficiency decreases

Engineering Contradiction:
Improvemanufacturing costVSAvoidnumber of manufacturing processes
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines multiple manufacturing steps into fewer processes. Specifically, the gate electrode and source/drain electrodes are formed in a single metal deposition and patterning step using the same mask, eliminating the need for separate M1 and M2 processes. The pixel electrode is simultaneously formed during the same patterning step, further reducing process count from 4+ to 2 processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The first mask serves multiple functions: it defines the gate electrode pattern, the source/drain electrode pattern, and the pixel electrode pattern all in one step. This multi-functional mask approach eliminates the need for separate masks for gate, source/drain, and pixel electrode formation, reducing both mask count and process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If conventional VA manufacturing process with at least four processes is used, then the display performance is achieved, but the manufacturing time increases and productivity decreases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidmanufacturing cycle time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple sequential manufacturing operations into parallel or simultaneous operations. The gate, source/drain, and pixel electrodes are all formed during the same metal deposition and etching cycle, reducing the total manufacturing cycle time and improving productivity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The mask design is prepared in advance to simultaneously define all electrode patterns (gate, source/drain, pixel electrode) in a single exposure and development step. This preliminary preparation of the multi-functional mask enables subsequent rapid fabrication without requiring multiple sequential patterning steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing costs and enhances efficiency by streamlining the process to two masks, improving the overall production efficiency and cost-effectiveness of the array substrate and liquid crystal panel.

Implementation Method 1

adopting a first mask to etch the first metal substrate to form a gate; adopting a second mask to etch the second metal layer and the active layer to form a source, a drain, and a pixel electrode

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10824031B2Manufacturing method of an array substrate comprising a source electrode, a drain electrode, and a pixel electrode that are configured to be directly exposed within a liquid crystal layer
Publication Date: 2020.11.03 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US10824031B2 patent drawing
  • US10824031B2 patent drawing
  • US10824031B2 patent drawing

AI summary

The present disclosure relates to an array substrate and the manufacturing method thereof, and a liquid crystal panel. The method includes forming a first metal substrate on a substrate; adopting a first mask to etch the first metal substrate to form a gate; forming a gate insulation layer, an active layer, and a second metal layer on the first metal layer in sequence; and adopting a second mask to etch the second metal layer and the active layer to form a source, a drain, and a pixel electrode. In this way, only two masks are adopted in the manufacturing process. Thus, the manufacturing process is enhanced, and the cost of the product is reduced.