Array Substrate Two-Phase Data Writing for High Frequency Displays
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Solution Overview
Problem
Current organic light-emitting display devices are limited in achieving high frequency displays due to their low-frequency OLED limitations, which are harmful to eyes and cannot meet the requirements of the rapidly developing electronic gaming industry.
Innovation Solution
An array substrate and method for driving a pixel-driving circuit that includes multiple scan lines, data lines, and pixel-driving circuits, where the data-writing phase is divided into two phases: the first phase writes data signals into parasitic capacitors, and the second phase uses scan signals to write these signals into drive control terminals, allowing for overlap between phases to increase drive frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single-phase data-writing method is used, then the device complexity is low, but the display frequency is limited to low frequency
Solution Approach 1:
The data-writing phase is divided into two distinct phases: a first phase for writing data signals to parasitic capacitors, and a second phase for writing to drive control terminals. This segmentation allows overlapping execution with scan line operations, thereby increasing display frequency while managing complexity through structured phase division.
Solution Approach 2:
Data signals are written to parasitic capacitors in advance during the first phase, before the actual data-writing to pixel circuits occurs in the second phase. This preliminary action enables time overlap with scan line operations, achieving high-frequency display without proportionally increasing overall system complexity.
2Productivity
If the data-writing phase is divided into two phases with overlap, then the display frequency increases to high frequency, but the device complexity increases
Solution Approach 1:
The first phase of data-writing is merged with the scan line operation timeline, allowing simultaneous execution. The parasitic capacitor charging occurs during the same time window as scan line activation, effectively combining two functions into overlapping time periods and achieving high productivity without linear complexity increase.
Solution Approach 2:
The two-phase data-writing process maintains continuous useful action by eliminating idle time between phases. The first phase prepares data in parasitic capacitors while the second phase writes to pixel circuits, ensuring uninterrupted data flow and continuous productivity improvement throughout the display refresh cycle.
3Stability of the object's composition
If data is written directly to drive control terminals, then the process is simple, but display uniformity is affected by threshold voltage variations
Solution Approach 1:
Parasitic capacitors serve as intermediary elements between the data signal source and the drive control terminals. Data signals are first written to these capacitors in the first phase, which then transfer the signals to pixel circuits in the second phase. This intermediary mechanism isolates threshold voltage variations and improves display uniformity while maintaining a manageable two-phase process structure.
4Speed
If the first phase overlaps with the second phase of previous rows, then the display frequency increases, but the timing control complexity increases
Solution Approach 1:
The overlapping of phases follows a periodic pattern where the first phase of each row systematically overlaps with the second phase of the previous row. This periodic timing structure creates a predictable, repeating cycle that increases display frequency while keeping timing control complexity manageable through regular, pattern-based synchronization rather than arbitrary timing adjustments.
Data Source
AI summary
An array substrate includes that: a data-writing phase of each row of the pixel-driving circuits is divided into a first phase and a second phase, in the first phase, a data signal of each data line is written into a parasitic capacitor on a data wiring electrically connected to a respective one of the row of the pixel-driving circuits, and in the second phase, the corresponding scan line transmits a scan signal to the row of the pixel-driving circuits, and the parasitic capacitor on each of the data wirings electrically connected to the row of the pixel-driving circuits writes the data signal into a drive control terminal of a respective one of the pixel-driving circuits; and the first phase of each row of the pixel-driving circuits at least partially overlaps with the second phase of a previous row of the pixel-driving circuits.