Array Substrate U-Shaped Semiconductor Film for Pixel Area Reduction

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Solution Overview

Problem

Existing array substrates for display devices, such as electrophoretic displays, face challenges in reducing the area per pixel due to the large number of transistors, scan lines, and signal lines, which hinders the achievement of higher definition.

Innovation Solution

The array substrate design includes a semiconductor film with a U-shaped configuration, intersecting first and second gate electrodes and a signal line, allowing for a reduced area layout while maintaining effective signal transmission, and a CMOS configuration with parallel n-channel and p-channel transistors to optimize pixel transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a CMOS configuration with multiple transistors, scan lines, and signal lines is used to achieve low power consumption, then power consumption is reduced, but the area per pixel increases

Engineering Contradiction:

Improvepower consumptionVSAvoidarea per pixel

Core Design Contradiction:

Use of energy by moving objectVSArea of stationary object

Solution Approach 1:

The pixel transistor is divided into multiple transistors (first n-channel transistor, second n-channel transistor, first p-channel transistor, second p-channel transistor) with separate gate electrodes, allowing independent control and optimized layout that reduces the overall pixel area while maintaining CMOS low-power operation

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Gate electrodes are configured to extend in directions intersecting the scan lines, and transistor channels are arranged to intersect with gate electrodes rather than running parallel, utilizing two-dimensional space more efficiently to reduce pixel area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Use of energy by moving object

If the number of transistors, scan lines, and signal lines per pixel is increased to achieve low power consumption, then power consumption is reduced, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidnumber of transistors and lines

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

Multiple gate electrodes are coupled to the same scan line, and multiple transistor channels intersect with gate electrodes from different scan lines, merging control functions while maintaining independent transistor operation for low-power CMOS operation

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Each transistor configuration with intersecting channels and gate electrodes serves multiple functions: signal transmission, charge storage, and switching control, reducing the need for separate dedicated components and simplifying the overall pixel structure

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11658188B2Array substrate and display device

Publication Date: 2023.05.23 MAGNOLIA WHITE CORP

AI summary

According to an aspect, an array substrate includes a first scan line, a second scan line, and a signal line. A semiconductor film has a coupling portion coupling one end of a first linear portion to one end of a second linear portion. Another end of the first linear portion of the semiconductor film and another end of the second linear portion of the semiconductor film are coupled to the signal line. In a plan view, the semiconductor film is disposed between the first scan line and the second scan line, the first linear portion intersects two first gate electrodes, and the second linear portion intersects two second gate electrodes.