Array Substrate Light-Blocking Layout to Prevent LTPO Vacuum Alarms

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In the fabrication of display panels, particularly those using low-temperature polycrystalline oxide (LTPO) processes, the use of a high-coverage photoresist for light-blocking bars leads to vacuum alarms due to gas production during doping processes, affecting the reliability of the display panel.

Innovation Solution

The array substrate design includes a first light-blocking pattern positioned in layers other than the first gate metal layer, reducing the width of the light-blocking bar while ensuring light-blocking requirements, thereby minimizing photoresist coverage and preventing vacuum alarms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a high-coverage photoresist is used for light-blocking bars to ensure light-blocking requirements, then light-blocking performance is improved, but vacuum alarms occur during doping processes due to gas production from excessive photoresist coverage

Engineering Contradiction:
Improvelight leakVSAvoidvacuum alarm
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The light-blocking function is segmented between two distinct components: the first light-blocking pattern (providing primary light blocking) and the first gate metal layer (providing additional light blocking). This segmentation allows reduction of photoresist coverage on individual components while maintaining cumulative light-blocking performance, thereby preventing vacuum alarms during doping processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first light-blocking pattern and the first gate metal layer are combined to form a composite light-blocking system. The first gate metal layer serves dual functions: as an electrical conductor for the transistor gate and as a secondary light-blocking layer. This merging reduces the need for extensive photoresist coverage while ensuring adequate light blocking performance.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If the width of the light-blocking bar is reduced to minimize photoresist coverage, then vacuum alarm risk is reduced, but light-blocking performance may be compromised

Engineering Contradiction:
Improvevacuum alarmVSAvoidlight leak
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The light-blocking solution extends into the vertical dimension by stacking the first light-blocking pattern and the first gate metal layer at different heights/zlevels. This multi-layer vertical arrangement provides cumulative light-blocking capability, allowing each individual layer to be thinner while maintaining overall light-blocking performance equivalent to or better than a single thick layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The light-blocking system uses a composite structure combining the first light-blocking pattern (optimized for light absorption/blocking) and the first gate metal layer (providing both electrical and optical blocking functions). This composite approach leverages the complementary properties of different materials and layers to achieve superior light-blocking performance with reduced photoresist coverage.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20260023294A1Array Substrate, Display Panel and Display Apparatus
Publication Date: 2026.01.22 BEIJING BOE CHUANGYUAN TECHNOLOGY CO LTD
  • US20260023294A1 patent drawing
  • US20260023294A1 patent drawing
  • US20260023294A1 patent drawing

AI summary

An array substrate includes sub-pixels located in a display area of the array substrate. Each sub-pixel includes a first transistor and a pixel electrode. The array substrate includes a base substrate; a first gate metal layer, a first source-drain metal layer, a planarization layer and a pixel electrode layer that are sequentially arranged on the base substrate; and first light-blocking patterns located on a side of the first gate metal layer away from the base substrate. The first source-drain metal layer includes a drain pattern of the first transistor. The pixel electrode layer includes pixel electrodes. A pixel electrode and a drain pattern of a first transistor belonging to a same sub-pixel are connected through a first via hole in the planarization layer. An orthographic projection of the first via hole on the base substrate is located within an orthographic projection of a first light-blocking pattern on the base substrate.