Array Substrate Layout With Adjustable Capacitor for Variable Refresh

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Solution Overview

Problem

Display apparatuses face challenges in achieving compatibility with high and low refresh rates, low-temperature startup capability, and large-angle display effects due to limitations from capacitors in the panel and shift register units.

Innovation Solution

The array substrate incorporates an adjustable capacitor and specific transistor configurations, including a second sub-pixel portion with an adjustable capacitor and protruding portions to maximize storage capacitance and adjust capacitance values, while optimizing the layout to alleviate interference and improve aperture ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a fixed capacitor is used in the panel and shift register unit, then the circuit structure is simple, but the display apparatus cannot achieve compatibility with high and low refresh rates and has poor low-temperature startup capability

Engineering Contradiction:
Improvecompatibility with high and low refresh ratesVSAvoidcapacitor structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies the dynamics principle by replacing fixed capacitors with adjustable capacitors that can dynamically change their capacitance values. The adjustable capacitor includes a semiconductor layer with variable capacitance characteristics, allowing the capacitor to adapt its capacitance value based on operating conditions such as refresh rate and temperature, thereby achieving compatibility with both high and low refresh rates while maintaining a relatively simple overall circuit structure.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by utilizing a semiconductor layer whose capacitance value can be varied through changes in voltage, temperature, or other physical parameters. The adjustable capacitor's capacitance value is modified by applying different voltages to the semiconductor layer, enabling the display apparatus to adapt to different refresh rates and temperature conditions without requiring completely different circuit configurations.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the capacitor size is increased to improve storage capacitance, then the low-temperature startup capability is improved, but the aperture ratio is reduced

Engineering Contradiction:
Improvelow-temperature startup capabilityVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent uses parameter changes to achieve variable capacitance values without increasing physical capacitor size. The adjustable capacitor utilizes a semiconductor layer whose capacitance can be tuned through voltage application, allowing the system to achieve equivalent or superior low-temperature startup capability with a smaller physical footprint, thereby preserving aperture ratio while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the capacitor is placed in various positions to maximize storage capacitance, then the low-temperature startup capability is improved, but the layout complexity and interference increase

Engineering Contradiction:
Improvelow-temperature startup capabilityVSAvoidlayout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by positioning the adjustable capacitor with its semiconductor layer in a specific location within the pixel structure where it can effectively provide the required capacitance for low-temperature startup. The capacitor is integrated into the pixel circuit in a manner that minimizes interference with adjacent structures while maintaining optimal electrical characteristics, thus achieving improved reliability without excessive layout complexity.

Inventive Principle:
Principle #3Local quality

4Illumination intensity

If the aperture ratio is increased, then the display brightness is improved, but the storage capacitance is reduced

Engineering Contradiction:
Improvedisplay brightnessVSAvoidstorage capacitance
Core Design Contradiction:
Illumination intensityVSQuantity of substance

Solution Approach 1:

The patent resolves this contradiction by using an adjustable capacitor with variable capacitance that can be optimized for different operating modes. The semiconductor layer's capacitance value can be dynamically adjusted to provide sufficient storage capacitance when needed (e.g., during low-temperature startup) while allowing the physical aperture area to remain large for optimal display brightness, thus decoupling the relationship between aperture ratio and storage capacitance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances compatibility with high and low refresh rates, improves low-temperature startup capability, and reduces color cast under large viewing angles by optimizing capacitor placement and transistor connections.

Implementation Method 1

an adjustable capacitor and specific transistor configurations, including a second sub-pixel portion with an adjustable capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12505814B2Array substrate, shift register unit and display apparatus
Publication Date: 2025.12.23 BEIJING BOE TECH DEV CO LTD
  • US12505814B2 patent drawing
  • US12505814B2 patent drawing
  • US12505814B2 patent drawing

AI summary

An array substrate, a shift register unit and a display apparatus are provided. The array substrate includes data lines, gate lines, first control signal lines and sub-pixels. The sub-pixel includes a first sub-pixel portion including a first pixel electrode and a first transistor, and a second sub-pixel portion including a second pixel electrode, a second transistor and a third transistor; the first transistor is connected with the first pixel electrode the second transistor and the third transistor are connected with the second pixel electrode, the first transistor and the second transistor are connected with a same gate line and a same data line, and the third transistor is connected with the first control signal line. The second sub-pixel portion includes an adjustable capacitor connecting with the third transistor, and the array substrate further includes a second control signal line connected with the adjustable capacitor.